PCF8545ATT datasheet(6/103 Pages) NXP

6 / 103 page

PCA8530

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Product data sheet

Rev. 2 — 25 September 2014

6 of 103

NXP Semiconductors

PCA8530

Automotive 102 x 4 Chip-On-Glass LCD segment driver

7.2 Pin description

Table 4.

Pin description

Input or input/output pins must always be at a defined level (VSS or VDD) unless otherwise specified.

Symbol

Type

Description

Backplane output pins

COM3

1 to 7, 190 to 195

output

LCD backplane

COM2

8 to 11, 186 to 189

COM1

117 to 120, 182 to 185

COM0

121 to 125, 178 to 181

Segment output pins

S101

126, 127

output

LCD segment

S100 to S51

128 to 177

S50 to S1

196 to 245

246, 247

VLCD pins

VLCDIN

12 to 15

supply

VLCD input

VLCDSENSE

16 to 18

input

VLCD regulation input

VLCDOUT

19 to 22

output

VLCD output

Test pins

23 to 25

output

not accessible; must be left open

26 to 30

input

not accessible; must be connected to T5

31, 32

output

not accessible; must be connected to T3

33, 34

output

not accessible; must be left open

58, 59

input

not accessible; must be connected to VSS1

60, 61

Supply pins

VSS2[1]

35 to 44

supply

ground supply

VSS3[1]

45 to 48

VSS1[1]

49 to 57

VDD1

74 to 78

supply

supply voltage 1 (analog and digital)

VDD3

79 to 82

supply

supply voltage 3 (analog)

VDD2

83 to 90

supply

supply voltage 2 (charge pump)

Oscillator, synchronization, addressing, and reset pins

CLK[2]

93 to 95

input/output

internal oscillator output, external oscillator input

OSC[2]

68, 69

input

clock (internal/external) selector

SYNC1[3]

96 to 98

input/output

charge pump synchronization for cascaded devices; must not be

connected if VLCD is externally supplied

SYNC0[3]

99 to 101

input/output

display synchronization for cascaded devices

RST

102, 103

input

active LOW reset input

62, 63

input

hardware device address selection for cascading;

• connect to VSS1 for logic 0

• connect to VDD1 for logic 1

64, 65

input

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