PCF8545ATT datasheet(82/103 Pages) NXP

номер детали	PCF8545ATT

подробное описание детали	Automotive 102 x 4 Chip-On-Glass LCD segment driver

PDF	103 Pages

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производитель	NXP [NXP Semiconductors]

домашняя страница	http://www.nxp.com

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PCA8530

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Product data sheet

Rev. 2 — 25 September 2014

82 of 103

NXP Semiconductors

PCA8530

Automotive 102 x 4 Chip-On-Glass LCD segment driver

15.2.2 Device synchronization

The SYNC0 and SYNC1 lines are provided to maintain the correct synchronization

between all cascaded PCA8530. (SYNC1 must not be connected when using an

externally supplied VLCD.) This synchronization is guaranteed after the Power-On Reset

(POR). SYNC0 and SYNC1 are organized as input/output pins.

Both, the internally generated clock frequency or, alternatively, an externally supplied

clock signal can be used in cascaded applications.

In cascaded applications that use the internal clock, the master PCA8530 with device

address A[1:0] = 00 must have the OSC pin connected to VSS1 and the COE bit is set

logic 1, so that this device uses its internal clock to generate a clock signal at the CLK pin.

(1) Is master (A0 connected to VSS1).

(2) Is slave (A0 connected to VDD1).

Fig 57. Cascaded configuration with two PCA8530 with internal VLCD and external clock

PCF8545ATT датащи(PDF) 82 Page - NXP Semiconductors