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TDF8599B датащи(PDF) 10 Page - NXP Semiconductors

номер детали TDF8599B
подробное описание детали  I2C-bus controlled dual channel 43 W/2 Ohm, single channel 85 W/1 Ohm class-D power amplifier with load diagnostics
PDF  54 Pages
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производитель  NXP [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo NXP - NXP Semiconductors

TDF8599B датащи(HTML) 10 Page - NXP Semiconductors

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NXP Semiconductors
TDF8599B
I2C-bus controlled dual channel 43 W/2 Ohm, single channel 85 W/1 Ohm class-D power amplifier with
load diagnostics
TDF8599B
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 2 — 23 August 2016
10 / 54
sets the oscillator frequency (fosc). In I2C-bus mode, this frequency can be varied by
± 10 %. Set bit IB1[D4] to logic 1 and bit IB1[D3] to either logic 0 (0.9 × fosc) or logic 1
(1.1 × fosc).
8.3.4 Phase lock operation (Slave mode)
In Slave mode, Phase-Locked Loop (PLL) operation can be used to reduce the jitter
effect of the external oscillator signal connected to pin OSCIO. Phase lock operation
is also needed to enable phase staggering, see Section 8.4.2. Phase lock operation is
enabled when the oscillator is in Slave mode by connecting two capacitors (CPLL_s and
CPLL_p) and a resistor (RPLL) between pin SSM and pin AGND (see Figure 8). Connecting
pin SSM to pin AGND disables phase lock operation and causes the slave to directly
use the external oscillator signal. Values for CPLL_s, CPLL_p and RPLL depend on the
desired loop bandwidth (BPLL) of the PLL. RPLL is given by: RPLL = 8.4 × BPLL Ω. The
corresponding values for CPLL_p and CPLL_s are given by Equation 3 and Equation 4:
(3)
Remark: CPLL_p is only needed when 1/4 π phase shift is selected. See Section 8.4.2 for
more detailed information.
(4)
When pin OSCIO is connected to a clock-master with Spread spectrum mode enabled,
the PLL loop bandwidth BPLL should be 100 × fSSM.
001aai776
100 µA
SSM
OSCSET
PLL
a. Off
Figure 8. Phase lock operation
001aai777
100 µA
PLL
OSCSET
RPLL
CPLL_p(1)
CPLL_s
SSM
(1) Only needed when 1/4 π phase shift is
selected.
b. On
Table 7 lists all oscillator modes.
Table 7. Oscillator modes
OSCSET pin
OSCIO pin SSM pin
Oscillator modes
Rosc > 26 kΩ
output
CSSM to pin AGND
master, spread spectrum
Rosc > 26 kΩ
output
shorted to pin AGND
master, no spread spectrum



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