TDF8599B datasheet(52/54 Pages) NXP

52 / 54 page

NXP Semiconductors

TDF8599B

I2C-bus controlled dual channel 43 W/2 Ohm, single channel 85 W/1 Ohm class-D power amplifier with

load diagnostics

TDF8599B

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 23 August 2016

52 / 54

Tables

Tab. 1.

Quick reference data .........................................2

Tab. 2.

Table 2. Ordering information ........................... 2

Tab. 3.

Table 3. Pin description .................................... 4

Tab. 4.

I2C-bus mode operation ....................................7

Tab. 5.

Non-I2C-bus mode operation ............................7

Tab. 6.

Mode setting pin OSCIO ...................................8

Tab. 7.

Oscillator modes ............................................. 10

Tab. 8.

Operation mode selection with the MOD pin ....11

Tab. 9.

Overview of protection types ...........................14

Tab. 10. Overview of TDF8599B protection circuits

and amplifier states .........................................16

Tab. 11. Available data on pins DIAG and CLIP ........... 17

Tab. 12. Interpretation of DC load detection bits ........... 19

Tab. 13. I2C-bus write address selection using pins

MOD and ADS ................................................ 22

Tab. 14. Instruction byte descriptions ............................24

Tab. 15. Phase shift bit settings ....................................24

Tab. 16. Description of data bytes ................................ 25

Tab. 17. Limiting values ................................................ 26

Tab. 18. Table 18. Thermal characteristics ................... 27

Tab. 19. Static characteristics ....................................... 27

Tab. 20. Switching characteristics ................................. 30

Tab. 21. Dynamic characteristics .................................. 31

Tab. 22. Filter component values .................................. 35

Tab. 23. SnPb eutectic process (from J-STD-020C) ..... 47

Tab. 24. Lead-free process (from J-STD-020C) ............ 47

Tab. 25. Table 25. Abbreviations .................................. 49

Tab. 26. Table 26. Revision history ...............................49

Figures

Fig. 1.

Block diagram ................................................... 3

Fig. 2.

Heatsink up (top view) pin configuration

TDF8599BTH .................................................... 4

Fig. 3.

Mode selection .................................................. 6

Fig. 4.

Clock frequency as a function of Rosc ..............8

Fig. 5.

Master and slave configuration ......................... 8

Fig. 6.

Spread spectrum mode .....................................9

Fig. 7.

Spread spectrum operation in Master mode ......9

Fig. 8.

Phase lock operation ...................................... 10

Fig. 9.

AD/BD modulation switching circuit .................12

Fig. 10.

AD modulation .................................................12

Fig. 11.

BD modulation .................................................12

Fig. 12.

Master and slave operation with 1/2 π phase

shift ..................................................................13

Fig. 13.

Parallel mode .................................................. 13

Fig. 14.

DC offset protection and diagnostic output ......15

Fig. 15.

Diagnostic output for short circuit conditions ....17

Fig. 16.

DC load detection circuit ................................. 18

Fig. 17.

DC load detection procedure .......................... 18

Fig. 18.

DC load detection limits .................................. 18

Fig. 19.

Recommended start-up sequence with DC

load detection enabled ....................................20

Fig. 20.

Start-up and shutdown timing in I2C-bus

mode with DC load detection .......................... 21

Fig. 21.

Start-up and shutdown timing in non-I2C-

bus mode ........................................................ 22

Fig. 22.

I2C-bus start and stop conditions ....................23

Fig. 23.

Data bits sent from Master microprocessor

(Mµp) ............................................................... 23

Fig. 24.

I2C-bus write ................................................... 23

Fig. 25.

I2C-bus read ................................................... 23

Fig. 26.

Po as a function of VP in stereo mode with

THD = 0.5 % ...................................................33

Fig. 27.

Po as a function of VP in stereo mode with

THD = 10 % ....................................................33

Fig. 28.

Po as a function of VP in stereo mode with

THD = 0.5 % ...................................................34

Fig. 29.

Po as a function of VP in stereo mode with

THD = 10 % ....................................................34

Fig. 30.

THD + N as a function of output power with

a 2 Ω load; VP = 14.4 V ................................. 36

Fig. 31.

THD + N as a function of output power with

a 4 Ω load; VP = 14.4 V ................................. 36

Fig. 32.

THD + N as a function of output power with

a 2 Ω load; VP = 24 V .................................... 36

Fig. 33.

THD + N as a function of output power with

a 4 Ω load; VP = 24 V .................................... 36

Fig. 34.

THD + N as a function of frequency with a

2 Ω load; VP = 14.4 V; BD modulation ............37

Fig. 35.

THD + N as a function of frequency with a

4 Ω load; VP = 14.4 V; BD modulation ............37

Fig. 36.

THD + N as a function of frequency with a

2 Ω load, BD modulation; VP = 24 V ...............37

Fig. 37.

Gain as a function of frequency ...................... 37

Fig. 38.

Output power as a function of supply voltage

with a 2 Ω load ............................................... 38

Fig. 39.

Output power as a function of supply voltage

with a 4 Ω load ............................................... 38

Fig. 40.

Channel separation as a function of

frequency with 1 W output power, BD

modulation .......................................................38

Fig. 41.

Channel separation as a function of

frequency with 10 W output power, BD

modulation .......................................................38

Fig. 42.

Power dissipation as a function of total

output power with both channels driven; VP

= 14.4 V .......................................................... 39

Fig. 43.

Efficiency as a function of total output power

with both channels driven; VP = 14.4 V ...........39

Fig. 44.

Power dissipation as a function of total

output power with both channels driven; VP

= 24 V ............................................................. 39

Fig. 45.

Efficiency as a function of total output power

with both channels driven; VP = 24 V ............. 39

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