TDF8599B datasheet(21/54 Pages) NXP

21 / 54 page

NXP Semiconductors

TDF8599B

I2C-bus controlled dual channel 43 W/2 Ohm, single channel 85 W/1 Ohm class-D power amplifier with

load diagnostics

TDF8599B

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 23 August 2016

21 / 54

8.6.3 Start-up and shutdown sequence

To prevent switch on or switch off ‘pop noise’, a capacitor (CSVRR) connected to pin

SVRR is used to smooth start-up and shutdown. During start-up and shutdown, the

output voltage tracks the voltage on pin SVRR. Increasing CSVRR results in a longer start-

up and shutdown time. Enhanced pop noise performance is achieved by muting the

amplifier until the SVRR voltage reaches its final value and the outputs start switching.

The value of capacitor connected to pin SEL_MUTE (CON) determines the unmute and

mute timing. The voltage on pin SEL_MUTE determines the amplifier gain. Increasing

CON increases the unmute and mute times. In addition, a larger CON value increases the

DC load detection cycle.

When the amplifier is switched off with an I2C-bus command or by pulling pin EN LOW,

the amplifier is first muted and then capacitor (CSVRR) is discharged.

In Slave mode, the device enters the off state immediately after capacitor (CSVRR) is

discharged. In Master mode, the clock is kept active by an additional delay (td(2)) of

approximately 50 ms to allow slave devices to enter the off state.

When an external clock is connected to pin OSCIO (in Slave mode), the clock must

remain active during the shutdown sequence for delay (td(1)) to ensure that the slaved

TDF8599B devices are able to enter the off state.

001aai790

VDDA

DIAG

ACGND

IB1[D0] and

IB2[D0] = 0

SEL_MUTE

SVRR

OUTn

td(2)

td(1)

td(mute-fgain)

mute delay

td(stb-mute)

twake

tdet(DCload)

td(3)

(1) Shutdown hold delay.

(2) Master mode shutdown delay.

(3) Shutdown delay.

Figure 20. Start-up and shutdown timing in I2C-bus mode with DC load detection

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