ADA4097-1BUJZ-R5 datasheet(23/31 Pages) AD

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Data Sheet

ADA4097-1/ADA4097-2

APPLICATIONS INFORMATION

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Rev. A | 23 of 31

LARGE RESISTOR GAIN OPERATION

The ADA4097-1/ADA4097-2 have approximately 3.5 pF of input

capacitance (CIN).

The parallel combination of the RF and RG on the inverting input

can combine with CIN to form a pole that can reduce bandwidth,

cause frequency response peaking, or produce oscillations (see

Figure 60). To mitigate these consequences, place a feedback

capacitor (CF) with a value of CF > CIN(RG/RF) in parallel with RF

for summing node impedances >200 kΩ (RF||RG > 200 kΩ). This

capacitor placement cancels the input pole and optimizes dynamic

performance (see Figure 59).

For applications where the noise gain is unity (RG→∞), and the

feedback resistor exceeds 200 kΩ, CF ≥ CIN. Optimize PCB layouts

to keep layout related summing node capacitance to an absolute

minimum.

Figure 59. Inverting Gain Schematic

Figure 60. Inverting Gain of 1, Small Signal Frequency Response, RF = RG = 1

MΩ

RECOMMENDED VALUES FOR VARIOUS

GAINS

Table 9 is a reference for determining various recommended gains

and associated noise performance. The total impedance seen at

the inverting input is kept to <200 kΩ for gains >1 to maintain ideal

small signal bandwidth.

Table 9. Gains and Associated Recommended Resistor Values (TA = 25°C)

Gain

RF (kΩ)

RG (kΩ)

CF (pF)

Approximate −3 dB Frequency (kHz)

Total System Noise (nV/√Hz at 1 kHz), Referred to Input

Not applicable

220

100

59.5

40.2

33.5

53.2

+10

53.2

−1

108

−1

100

119

−1

1000

215

−2

−5

49.9

64.2

−10

100

58.5

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