ADA4097-1BUJZ-R5 datasheet(25/31 Pages) AD

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Data Sheet

ADA4097-1/ADA4097-2

APPLICATIONS INFORMATION

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Rev. A | 25 of 31

POWER DISSIPATION AND THERMAL

SHUTDOWN

The ADA4097-1/ADA4097-2 can drive heavy loads on power sup-

plies up to ±25 V. Therefore, ensure that TJ on the IC does not

exceed 175°C. See Table 4 for the θJA of each package type.

Junction temperatures exceeding 125°C promote accelerated ag-

ing. Reliability of the ADA4097-1/ADA4097-2 may be impaired if

the junction temperature exceeds 175°C. If the junction temperature

exceeds 175°C, the ADA4097-1/ADA4097-2 has a final safety

measure in the form of a thermal shutdown that shuts off the

output stage and reduces the internal device currents. When this

thermal shutdown function triggers, the output remains disabled in

a high impedance state until the junction temperature drops 20°C.

Persistent heavy loads and elevated ambient temperatures can

cause the ADA4097-1/ADA4097-2 to oscillate in and out of thermal

shutdown depending on the power dissipated on the die, until the

heavy load is removed (see Figure 63).

Figure 63. ADA4097-1/ADA4097-2 Cycling In and Out of Thermal Shutdown

It is not recommended to operate near the maximum junction

temperature.

Typically, TJ can be estimated from TA and the device power

dissipation (PD × θJA), as shown in the following equation:

TJ = TA + PD × θJA

The power dissipation in the IC varies as a function of supply

voltage, the output voltage, and load resistance. For a given supply

voltage, the worst case power dissipation (PD(MAX)) in the IC occurs

when the supply current is maximum, and the output voltage is at

half of either supply voltage.

PDMAX =VSISMAX+ VSY22RLOAD

For a given supply voltage, use Figure 64 as a guide for estimating

the minimum load resistance that the ADA4097-1/ADA4097-2 can

drive for a given supply voltage and a given rise in junction temper-

ature (ΔTJ). For example, to limit ΔTJ to 50°C, the load driven on

the ±15 V supplies (+30 V total supply) must not be lower than

0.8 kΩ. Note that it is assumed that θJA is 192°C/W for the 6-lead

TSOT package only.

Figure 64. Minimum Load Resistance for Given ΔTJ and VSY

CIRCUIT LAYOUT CONSIDERATIONS

Careful and deliberate attention to detail when laying out the

ADA4097-1/ADA4097-2 boards yields optimal performance. Power

supply bypassing, parasitic capacitance, and component selection

all contribute to the overall performance of the amplifier.

POWER SUPPLY BYPASSING

On single supplies, solder the −VS supply pin directly to a low

impedance ground plane. Bypass the +VS pin to a low impedance

ground plane with a low effective series resistance (ESR) multilayer

ceramic capacitor (MLCC) of 0.1 µF, typically, as close to the ±VS

supply pins as possible. When driving heavy loads, add 10 µF of

supply capacitance. When using split supplies, these conditions are

applicable to the −VS supply pin.

The ADA4097-1/ADA4097-2 have an internal current source of

~0.6 μA on the SHDN pin (ADA4097-1) and the SHDNx pins

(ADA4097-2, the 10-lead LFCSP only) to pull the pins down to

−VS and to place the op amps in the default amplifying state. If

the shutdown state is not required, hard tie the SHDN pin and

the SHDNx pins to the −VS pin. If the SHDN pin and the SHDNx

pins are left floating or driven by a source with significant source

impedance (>100 Ω), bypass the −VS supply pin with a small, 1 nF

capacitor to prevent stray signals from coupling on the SHDN pin

and the SHDNx pins, which can inadvertently trigger shutdown.

GROUNDING

Use ground and power planes where possible to reduce the re-

sistance and inductance of the supply and ground returns. Place

bypass capacitors as close as possible to the ±VS supply pins, with

the other ends connected to the ground plane. It is recommended

to use a bypass capacitor of at least 0.1 µF when driving light

loads (load currents < 100 µA), and more capacitance when driving

heavier loads. Routing from the output to the load and return to the

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