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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SPC58NH84C5 датащи(PDF) 101 Page - STMicroelectronics |
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SPC58NH84C5 датащи(HTML) 101 Page - STMicroelectronics |
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101 / 147 page  DS12304 Rev 5 101/147 SPC58EHx, SPC58NHx Electrical characteristics 109 Figure 36. RMII transmit signal timing diagram 4.16.3.8 RGMII signal timing The RGMII interface uses Double Data Rate (DDR) data transfer scheme; it requires that the clock signal is delayed against the data and control signals. This RGMII interface is compliant with the delay mode Delay on Source (DoS), where the transmitter device already provides a delayed clock signal. For detailed AC specifications, refer to chapter 7.3 “Signal timing parameters in DoS mode” of specification “OPEN Alliance RGMII EPL (Electrical-Physical Layer) Recommendations” standard v2.3. 4.16.4 FlexRay timing This section provides the FlexRay Interface timing characteristics for the input and output signals. These are recommended numbers as per the FlexRay EPL v3.0 specification, and subject to change per the final timing analysis of the device. Table 53. RMII transmit signal timing Symbol C Characteristic Value Unit Min Max R5 CC D REF_CLK to TXD[1:0], TX_EN invalid 2 — ns R6 CC D REF_CLK to TXD[1:0], TX_EN valid — 15 ns R7 CC D REF_CLK pulse width high 35% 65% REF_CLK period R8 CC D REF_CLK pulse width low 35% 65% REF_CLK period R6 REF_CLK (input) TXD[1:0] (outputs) TX_EN R5 R7 R8 |
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