MCF5373CAB180 datasheet(5/46 Pages) NXP

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Hardware Design Considerations

MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4

Freescale Semiconductor

Hardware Design Considerations

3.1

PLL Power Filtering

To further enhance noise isolation, an external filter is strongly recommended for PLL analog VDD pins. The filter shown in

Figure 2 should be connected between the board VDD and the PLLVDD pins. The resistor and capacitors should be placed as

close to the dedicated PLLVDD pin as possible.

Figure 2. System PLL VDD Power Filter

3.2

USB Power Filtering

To minimize noise, external filters are required for each of the USB power pins. The filter shown in Figure 3 should be

connected between the board EVDD or IVDD and each of the USBVDD pins. The resistor and capacitors should be placed as

close to the dedicated USBVDD pin as possible.

Figure 3. USB VDD Power Filter

NOTE

In addition to the above filter circuitry, a 0.01 F capacitor is also recommended in parallel

with those shown.

3.3

Supply Voltage Sequencing and Separation Cautions

The relationship between SDVDD and EVDD is non-critical during power-up and power-down sequences. SDVDD (2.5V or

3.3V) and EVDD are specified relative to IVDD.

3.3.1

Power Up Sequence

If EVDD/SDVDD are powered up with IVDD at 0 V, the sense circuits in the I/O pads cause all pad output drivers connected to

the EVDD/SDVDD to be in a high impedance state. There is no limit on how long after EVDD/SDVDD powers up before IVDD

must powered up. IVDD should not lead the EVDD, SDVDD, or PLLVDD by more than 0.4 V during power ramp-up or there is

Board IVDD

0.1 µF

PLL VDD Pin

10 µF

GND

Board EVDD

0.1 µF

USB VDD Pin

10 µF

GND

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