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MCF5373CAB180 датащи(PDF) 27 Page - NXP Semiconductors |
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MCF5373CAB180 датащи(HTML) 27 Page - NXP Semiconductors |
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27 / 46 page ![]() Electrical Characteristics MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4 Freescale Semiconductor 27 Figure 13. GPIO Timing 5.9 Reset and Configuration Override Timing Figure 14. RESET and Configuration Override Timing NOTE Refer to the CCM chapter of the MCF5373 Reference Manual for more information. Table 13. Reset and Configuration Override Timing Num Characteristic Symbol Min Max Unit R1 RESET Input valid to FB_CLK High tRVCH 9— ns R2 FB_CLK High to RESET Input invalid tCHRI 1.5 — ns R3 RESET Input valid Time 1 1 During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously to the system. Thus, RESET must be held a minimum of 100 ns. tRIVT 5— tCYC R4 FB_CLK High to RSTOUT Valid tCHROV —10 ns R5 RSTOUT valid to Config. Overrides valid tROVCV 0— ns R6 Configuration Override Setup Time to RSTOUT invalid tCOS 20 — tCYC R7 Configuration Override Hold Time after RSTOUT invalid tCOH 0— ns R8 RSTOUT invalid to Configuration Override High Impedance tROICZ —1 tCYC G1 FB_CLK GPIO Outputs G2 G3 G4 GPIO Inputs R1 R2 FB_CLK RESET RSTOUT R3 R4 R8 R7 R6 R5 Configuration Overrides*: R4 (RCON, Override pins]) |
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