DLPC3421 datasheet(24/63 Pages) TI

24 / 63 page

6.17 Other Timing Requirements

MIN

MAX

UNIT

trise, all(1) (2)

20% to 80% reference points

tfall, all(1) (2)

80% to 20% reference points

trise, PARKZ(2)

20% to 80% reference points

150

tfall, PARKZ(2)

80% to 20% reference points

150

tw, GPIO_08 (PROJ_ON) pulse width low(3)

200

I2C baud rate

100

kHz

(1)

Unless noted elsewhere, the following signal transition times are for all DLPC34xx signals.

(2)

This is the recommended signal transition time to avoid input buffer oscillations.

(3)

When the controller is turned off by setting PROJ_ON low, PROJ_ON must not be brought high again for at least 200 ms. View Section

9.3 for additional requirements.

6.18 DMD Sub-LVDS Interface Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tR (1)

Differential output rise time

250

tF (1)

Differential output fall time

250

tswitch

DMD HS clock switching rate

1200

Mbps

fclock

DMD HS clock frequency

600

MHz

DCout

DMD HS clock output duty cycle

45%

50%

55%

(1)

Rise and fall times are defined for the differential VOD signal as shown in Figure 6-2.

6.19 DMD Parking Switching Characteristics

See (2)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tpark

Normal park time(1)

tfast park

Fast park time(3)

µs

(1)

Normal park time is defined as how long it takes the DLPC34xx controller to complete the parking of the DMD after it receives the

normal park request (GPIO_08 goes low).

(2)

The oscillator and power supplies must remain active for at least the duration of the park time. The power supplies must additionally

be held on for a time after parking is completed to satisfy DMD requirements. See Section 9.2 and the appropriate DMD or PMIC

datasheet for more information.

(3)

Fast park time is defined as how long it takes the DLPC34xx controller to complete the parking of the DMD after it receives the fast

park request (PARKZ goes low).

6.20 Chipset Component Usage Specification

The DLPC3421 is a component of a DLP chipset. Reliable function and operation of the DLP chipset requires

that it be used with all components (DMD, PMIC, and controller) of the applicable DLP chipset.

Table 6-1. DLPC3421 Supported DMDs and PMICs

DLPC3421 DLP Chipset

DMD

DLP160CP

PMIC

DLPA2000

DLPA2005

DLPC3421

DLPS231 – OCTOBER 2021

www.ti.com

Submit Document Feedback

Product Folder Links: DLPC3421

DLPC3421 датащи(PDF) 24 Page - Texas Instruments

DLPC3421 датащи(HTML) 24 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

датащи скачать

ссылки URL