DLPC3421 datasheet(30/63 Pages) TI

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Host Processor

DSI Transmitter

DataN+

DataN±

DLPC34xx

DSI Receiver

Data0+

Data0±

Clock+

Clock±

DataN+

DataN±

Data0+

Data0±

Clock+

Clock±

- one clock lane

- one bi-directional data lane (Data0)

- up to three additional uni-directional data lanes (Data1, Data2, and Data3)

Figure 7-4. DSI High Level View

The differential DSI clock lane (DCLKN and DCLKP) must be in the LP11 (Idle) state upon the de-assertion

of RESETZ (zero-to-one transition) and must remain in this state until HOST_IRQ is de-asserted (one-to-zero

transition) to ensure proper DSI initialization.

The controller requires differential data lane '0' (DD0N:DD0P) for DSI operation. The three remaining data lanes

are optional depending on the desired input resolution and frame rate. Not all display resolutions and frame rates

are supported without using all four data lanes.

The state of GPIO (2:1) pins upon the de-assertion of RESETZ (zero-to-one transition) determines the number of

DSI data lanes that are enabled for both LP and HS bus operation.

DSI supported data transfer formats are as follows:

• 24-bit RGB888 - each pixel uses 3 bytes

• 18-bit RGB666 - each pixel packed into 2 or more bytes

• 18-bit RGB666 - each pixel loosely packed into 3 bytes

• 16-bit 4:2:2 YCbCr - each pixel uses 2 bytes

DLPC3421

DLPS231 – OCTOBER 2021

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DLPC3421 датащи(PDF) 30 Page - Texas Instruments