DLPC3421 datasheet(12/63 Pages) TI

12 / 63 page

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

V(VDD)

Core power 1.1 V (main 1.1 V)

1.045

1.10

1.155

V(VDDLP12)

DSI PHY low power mode driver supply

See (3) (4)

1.045

1.10

1.155

V(VCC18)

All 1.8-V I/O power:

(1.8-V power supply for all I/O pins except the host

or parallel interface and the SPI flash interface. This

includes RESETZ, PARKZ LED_SEL, CMP_OUT, GPIO,

IIC1, TSTPT, and JTAG pins.)

1.64

1.80

1.96

V(VCC_INTF)

Host or parallel interface I/O power: 1.8 to 3.3 V (includes

IIC0, PDATA, video syncs, and HOST_IRQ pins)

See (1)

1.64

1.80

1.96

2.28

2.50

2.72

3.02

3.30

3.58

V(VCC_FLSH)

Flash interface I/O power: 1.8 to 3.3 V

See (1)

1.64

1.80

1.96

2.28

2.50

2.72

3.02

3.30

3.58

V(VDD_PLLM)

MCG PLL 1.1-V power

See (2)

1.025

1.100

1.155

V(VDD_PLLD)

DCG PLL 1.1-V power

See (2)

1.025

1.100

1.155

Operating ambient temperature(5)

–30

°C

Operating junction temperature

–30

105

°C

(1)

These supplies have multiple valid ranges.

(2)

The minimum voltage is lower than other 1.1-V supply minimum to enable additional filtering. This filtering may result in an IR drop

across the filter.

(3)

It is recommended that VDDLP12 rail is tied to the VDD rail. The DSI LP supply (VDDLP12) is only used for read responses from the

controller which are not supported. Because of this, a separate 1.2-V rail is not required. If a separate 1.2-V supply is already being

used to power this rail, a voltage tolerance of ±6.67% is allowed on this separate 1.2-V supply.

(4)

When the DSI-PHY LP supply (VDDLP12) is fed from a supply separate from VDD, the VDDLP12 power must sequence ON after the

1.1-V core supply and must sequence OFF before the 1.1-V core supply.

(5)

The operating ambient temperature range assumes 0 forced air flow, a JEDEC JESD51 junction-to-ambient thermal resistance value

at 0 forced air flow (RθJA at 0 m/s), a JEDEC JESD51 standard test card and environment, along with minimum and maximum

estimated power dissipation across process, voltage, and temperature. Thermal conditions vary by application, and this affects RθJA.

Thus, maximum operating ambient temperature varies by application.

•

Ta_min = Tj_min – (Pd_min × RθJA) = –30°C – (0.0 W × 30.3°C/W) = –30°C

•

Ta_max = Tj_max – (Pd_max × RθJA) = +105°C – (0.348 W × 30.3°C/W) = +94.4°C

6.4 Thermal Information

THERMAL METRIC(1)

DLPC3421

UNIT

ZVB (NFBGA)

176 PINS

RθJC

Junction-to-case top thermal resistance

11.2

°C/W

RθJA

Junction-to-air thermal

resistance

at 0 m/s of forced airflow(2)

30.3

°C/W

at 1 m/s of forced airflow(2)

27.4

at 2 m/s of forced airflow(2)

26.6

ψJT

Temperature variance from junction to package top center temperature, per unit power

dissipation(3)

0.27

°C/W

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2)

Thermal coefficients abide by JEDEC Standard 51. RθJA is the thermal resistance of the package as measured using a JEDEC defined

standard test PCB. This JEDEC test PCB is not necessarily representative of the DLPC34xx PCB and thus the reported thermal

resistance may not be accurate in the actual product application. Although the actual thermal resistance may be different, it is the best

information available during the design phase to estimate thermal performance.

(3)

Example: (0.5 W) × (0.2°C/W) ≈ 0.1°C temperature rise.

DLPC3421

DLPS231 – OCTOBER 2021

www.ti.com

Submit Document Feedback

Product Folder Links: DLPC3421

DLPC3421 датащи(PDF) 12 Page - Texas Instruments

DLPC3421 датащи(HTML) 12 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

датащи скачать

ссылки URL