DLPC3421 datasheet(9/63 Pages) TI

9 / 63 page

Table 5-7. GPIO Peripheral Interface (continued)

PIN(1)

I/O

TYPE(3)

DESCRIPTION(2)

NAME

NO.

GPIO_01

C15

I/O

General purpose I/O 01 (hysteresis buffer). Options:

SPI1_CLK (output): SPI1 clock signal. This pin is typically connected to the DLPAxxxx SPI_CLK

pin.

Optional DSI Bus Width Config 0 (input): The controller samples this pin during boot and is used

to define the number of lanes used for DSI operation. Requires an external pullup or pulldown

resistor to configure as defined in Table 5-8. After boot, this GPIO pin will continue to be used as

SPI1_CLK. Select the external pullup or pulldown resistor to not interfere.

GPIO_00

C14

I/O

General purpose I/O 00 (hysteresis buffer). SPI1_DIN (input): SPI1 data input signal. This pin is

typically connected to the DLPAxxxx SPI_DOUT pin.

(1)

GPIO pins must be configured through software for input, output, bidirectional, or open-drain operation. Some GPIO pins have one or

more alternative use modes, which are also software configurable. An external pullup resistor is required for each signal configured as

open-drain.

(2)

General purpose I/O for the DLPC3421 controllers. These GPIO pins are software configurable.

(3)

See Table 5-11 for type definitions.

Table 5-8. GPIO_01 and GPIO_02

GPIO_02

GPIO_01

Number of DSI Data

Lanes

DSI Lane Config 1

DSI Lane Config 0

Table 5-9. Clock and PLL Support

I/O

TYPE(1)

DESCRIPTION

NAME

NO.

PLL_REFCLK_I

Reference clock crystal input. If an external oscillator is used instead of a crystal, use

this pin as the oscillator input.

PLL_REFCLK_O

Reference clock crystal return. If an external oscillator is used instead of a crystal,

leave this pin unconnected (floating with no added capacitive load).

(1)

See Table 5-11 for type definitions.

Table 5-10. Power and Ground

I/O

TYPE

DESCRIPTION

NAME

NO.

VDD

C5, D5, D7,

D12, J4,

J12, K3, L4,

L12, M6,

M9, D9,

D13, F13,

H13, L13,

M10, D3, E3

—

PWR

Core 1.1-V power (main 1.1 V)

VDDLP12

—

PWR

DSI PHY Low Power mode driver supply. It is recommended to externally

tie this pin to VDD.

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