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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DLPC3421 датащи(PDF) 37 Page - Texas Instruments |
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DLPC3421 датащи(HTML) 37 Page - Texas Instruments |
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37 / 63 page  7.3.7 DMD Interface The DLPC34xx controller DMD interface consists of one high-speed (HS), 1.8-V sub-LVDS, output-only interface and one low speed (LS), 1.8-V LVCMOS SDR interface with a typical fixed clock speed of 120 MHz. 7.3.7.1 Sub-LVDS (HS) Interface Internal software selection allows the controller to support multiple DMD interface swap configurations. These options can improve board layout by remapping specific combinations of DMD interface lines to other DMD interface lines as needed. Table 7-8 shows the four options available for the DLP160CP DMD. Table 7-8. DLP160CP (0.16 nHD) DMD - Controller to 4-Lane DMD Pin Mapping Options DLPC3421 Controller 4-LANE DMD ROUTING OPTIONS DMD PINS Option 1 Swap Control = x0 Option 2 Swap Control = x2 Option 3 Swap Control = x1 Option 4 Swap Control = x3 HS_WDATA_D_P HS_WDATA_D_N HS_WDATA_E_P HS_WDATA_E_N HS_WDATA_H_P HS_WDATA_H_N HS_WDATA_A_P HS_WDATA_A_N Input DATA_p_0 Input DATA_n_0 HS_WDATA_C_P HS_WDATA_C_N HS_WDATA_F_P HS_WDATA_F_N HS_WDATA_G_P HS_WDATA_G_N HS_WDATA_B_P HS_WDATA_B_N Input DATA_p_1 Input DATA_n_1 HS_WDATA_F_P HS_WDATA_F_N HS_WDATA_C_P HS_WDATA_C_N HS_WDATA_B_P HS_WDATA_B_N HS_WDATA_G_P HS_WDATA_G_N Input DATA_p_2 Input DATA_n_2 HS_WDATA_E_P HS_WDATA_E_N HS_WDATA_D_P HS_WDATA_D_N HS_WDATA_A_P HS_WDATA_A_N HS_WDATA_H_P HS_WDATA_H_N Input DATA_p_3 Input DATA_n_3 www.ti.com DLPC3421 DLPS231 – OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: DLPC3421 |
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