ZL30264 datasheet(13/93 Pages) MICROCHIP

13 / 93 page

ZL30264-ZL30267

Data Sheet

DS20006555A

The crystal, traces, and two external capacitors sites (if included) should be placed on the board as close as

possible to the XA and XB pins to reduce crosstalk of active signals into the oscillator. Also no active signals should

be routed under the crystal circuitry.

Note: Crystals have temperature sensitivies that can cause frequency changes in response to ambient temperature

changes. In applications where significant temperature changes are expected near the crystal, it is recommended

that the crystal be covered with a thermal cap, or an external XO or TCXO should be used instead.

Table 2 - Crystal Selection Parameters

Parameter

Symbol

Min.

Typ.

Max.

Units

Crystal Oscillation Frequency1

fOSC

MHz

Shunt Capacitance

Load Capacitance3

Equivalent Series Resistance

(ESR)2

fOSC < 40MHz



fOSC > 40MHz



Maximum Crystal Drive Level

100

100, 200,

300

W

Note 1:

Higher frequencies give lower output jitter, all else being equal.

Note 2:

These ESR limits are chosen to constrain crystal drive level to less than 100

W. If the crystal can tolerate a drive level greater than

100

W then proportionally higher ESR is acceptable.

Note 3:

For crystals with 100

W max drive level: (a) f

OSC>55MHz and CL12pF is not supported, and (b) fOSC>45MHz and CL16pF is not

supported. Crystals with max drive level of 200

W or higher do not have these limitations.

Parameter

Symbol

Min.

Typ.

Max.

Units

Crystal Frequency Stability vs. Power Supply

fFVD

0.2

0.5

ppm per 10%

 in VDD

Any known frequency inaccuracy of the crystal can be compensated in the APLL by adjusting the APLL's fractional

feedback divider value (AFBDIV) by ppb or ppm to compensate for crystal frequency error.

5.3.3

Clock Doublers

Figure 1

shows an optional clock doubler (“x2” block) following the crystal driver block. This XA doubler, which is

enabled by setting MCR2.DBL=1, can be used to double the frequency of the internal crystal driver circuit or a

20MHz to 78.125MHz clock signal on the XA pin. For input clock frequencies from 25MHz to 78.125MHz the duty

cycle of the signal can be anywhere in the 40% to 60% range. For input clock frequencies from 20MHz to 25MHz

the duty cycle must be in the 45% to 55% range. Figure 1 also shows an optional doubler at the input of each

APLL. This APLL input doubler, which is enabled by setting ACR1.INDBL=1 for APLL1 or A2CR1.INDBL=1 for

APLL2, can be used to double the frequency of any of the inputs. The following table shows scenarios when the

clock doubler can be used.

Scenario

With Crystal

With XO or Clock Signal

APLL, Integer Multiply

Yes1

Maybe1

APLL, Fractional Multiply

Yes

NCO

Yes

Spread-Spectrum

Yes

APLL bypass path

No2

Note 1: For APLL integer multiplication, use of the doubler is application-dependent. On the positive side, use of the

doubler reduces random jitter. On the negative side, the doubler causes a spur at the XA frequency (but this spur may be

outside the band of interest for the application).

Note 2: The signal generated by the doubler has a very narrow and variable pulse width and therefore it is not

recommended to connect the doubler signal directly to the OCx outputs using an APLL bypass path. The doubler signal is

fine as an input to the APLL, which filters the duty cycle distortion and produces a 50% duty cycle output.

Note 3: Using both doublers in series to double the XA-doubled signal is not supported.

5.3.4

Ring Oscillator (for Auto-Configuration)

After reset the internal auto-configuration boot controller is clocked by an internal ring oscillator. After auto-

configuration is complete (GLOBISR.BCDONE=1) the ring oscillator can be disabled by setting MCR1.ROSCD=1.

The device’s processor interface is asynchronous and does not require the ring oscillator.

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