ZL30264 datasheet(21/93 Pages) MICROCHIP

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ZL30264-ZL30267

Data Sheet

DS20006555A

configured for LVPECL output with standard 2.0V common-mode voltage by seting OCxDIFF.VCM for 2.0V and

setting OCxREG.VREG appropriately.

In both LVDS mode and programmable differential mode the output driver requires a DC path through a 100



resistor between OCxP and OCxN for proper operation. This resistor is usually placed as close as possible to the

receiver inputs to terminate the differential signal. If the receiver requires a common-mode voltage that cannot be

matched by the output driver then the POS and NEG signals can be AC-coupled to the receiver after the 100



resistor.

HCSL mode requires a DC path through a 50

 resistor to ground on each of OCxP and OCxN. Note that each of

the OCxDIFF.VCM, OCxDIFF.VOD and OCxREG.VREG register fields has a particular setting required for HCSL

signal format. See the descriptions of these fields for details.

Outputs are grouped into six power supply banks, VDDOA through VDDOF to allow CMOS or HSTL signal swing

from 1.5V to 3.3V for glueless interfacing to neighboring components. 10-output products have outputs grouped

into banks in a 2-1-2-2-1-2 arrangement, as shown in Figure 1. 6-output products have one output per bank. If

OCSF is set to HSTL mode then a 1.5V power supply voltage should be used to get a standards-compliant HSTL

output. Note that LVDS, LVPECL and HCSL signal formats must have a power supply of 2.5V or 3.3V. Also note

that VDDO voltage must not exceed VDDH voltage.

5.6.2

Output Frequency Configuration

The frequency of each output is determined by the configuration of the APLL, the

APLL’s output dividers, and the

per-output dividers. Each bank of outputs can be connected to

either APLL’s integer divider or fractional divider

using the appropriate field in the OCMUX registers.

Each output has two output dividers, a 7-bit medium-speed divider (OCxCR1.MSDIV) and a 24-bit low-speed

output divider (LSDIV field in the OCxDIV registers). These dividers are in series, medium-speed divider first then

output divider. These dividers produce signals with 50% duty cycle for all divider values including odd numbers.

The low-speed divider can only be used if the medium-speed divider is used (i.e. OCxCR1.MSDIV>0). The maxium

input frequency to the medium-speed divider is 750MHz.

Since each output has its own independent dividers, the device can output families of related frequencies that have

an APLL output frequency as a common multiple. For example, for Ethernet clocks, a 625MHz APLL output clock

can be divided by four for one output to get 156.25MHz, divided by five for another output to get 125MHz, and

divided by 25 for another output to get 25MHz. Similarly, for SDH/SONET clocks, a 622.08MHz APLL output clock

can be divided by 4 to get 155.52MHz, by 8 to get 77.76MHz, by 16 to get 38.88MHz or by 32 to get 19.44MHz.

Two Different Frequencies in 2xCMOS Mode

When an output is in 2xCMOS mode it can be configured to have the frequency of the OCxN clock be an integer

divisor of the frequency of the OCxP clock. Examples of where this can be useful:

•

125MHz on OCxP and 25MHz on OCxN for Ethernet applications

•

77.76MHz on OCxP and 19.44MHz on OCxN for SONET/SDH applications

• 25MHz on OCxP and 1Hz (i.e. 1PPS) on OCxN for telecom applications with Synchronous Ethernet and

IEEE1588 timing

An output can be configured to operate like this by setting the LSDIV value in the OCxDIV registers to OCxP_freq /

OCxN_freq - 1 and setting OCxCR3.LSSEL=0 and OCxCR3.NEGLSD=1. Here are some notes about this dual-

frequency configuration option:

• In this mode only the medium speed divider is used to create the OCxP frequency. The low-

speed divider is then used to divide the OCxP frequency down to the OCxN frequency. This

means that the lowest OCxP frequency is the APLL divider output frequency divided by 128.

• An additional constraint is that the medium-speed divider must be configured to divide by 2 or

more (i.e. must have OCxCR1.MSDIV

1).

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