ZL30264 datasheet(91/93 Pages) MICROCHIP

91 / 93 page

ZL30264-ZL30267

Data Sheet

DS20006555A

Revision

Description

aligning clocks from IntDiv with clocks from FracDiv is not supported.

In section 5.9 added new subsection 5.9.1 to guide users in the use of external RC reset

circuits.

19-Jan-2018

In the F1REM1

FREM must be set to 0.

”

In the F1DEN1

In the F1BP

must be set to 1.

”

In the AFBREM1

IIn the AFBBP

AFBDEN must be set to 1.

”

29-May-2018

On page 1 and in section 2.3 changed wording to indicate PCIe 1-4 compliance.

In OCxCR3.NEGLSD description added to note that OCxCR3.LSSEL must be 0 to set

NEGLSD=1.

14-Sep-2018

In Table 17, corrected typo for "Input-to-Output Propagation Delay, from IC3 input" in the Note

4 row where the max of 2.8 was less than typical of 3.4. Corrected the max to 3.8.

In the OCxCR2.OCSF description, deleted "(must have VDDOx=VDDH=3.3V)" from the HCSL

decode.

Updated Table 10 Note 1 and Table 11 Note 1 and added cross reference to Figure 17 parts a)

and b).

Updated Figure 17 to include new part c) and added noted about part c) below the figure.

In section 5.9.1 second paragraph added need for current-limiting series resistor between

source of reset signal and device RSTN pin.

In Table 1 pin descriptions for AC0/GPIO0, AC1/GPIO1, AC2/GPIO2 and TEST/GPIO3 added

note.

01-Oct-2018

In Table 15:

• Reduced integer output divider PCIe 3.0 jitter to 0.08 typical, 0.10 max (ps RMS) and added

new row for PCIe 4.0 jitter.

• Reduced fractional output divider PCIe 3.0 jitter to 0.09 typical, 0.12 max (ps RMS) and

added new row for PCIe 4.0 jitter.

• Added PCIe sentence to Note 8 and deleted second sentence of Note 6.

29-Sep-2020

In Table 12 changed max VOD from 0.86V to 0.95V, changed min VOD from 0.62V to 0.6V and

changed VCM spec to VOD / 2.

18-Dec-2020

On pages 1 and 5 added PCIe 5 to the lists of PCIe versions.

In Table 15 added new rows for PCIe 5 jitter.

17-Jun-2021

Updated Microsemi wording and branding to Microchip throughout.

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