ZL30264 datasheet(72/93 Pages) MICROCHIP

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ZL30264-ZL30267

Data Sheet

DS20006555A

OCxPH

Output Clock x Phase Adjust Register

OC1: 209h, OC2: 219h, OC3: 229h, OC4: 239h, OC5: 249h

OC6: 259h, OC7: 269h, OC8: 279h, OC9: 289h, OC10: 299h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

—

PHADJ[3:0]

Default

Bits 3 to 0: Phase Adjust Value (PHADJ[3:0]). This field can be used to adjust the phase of an output clock vs.

the phase of other clock outputs. The adjustment is in units of bank source clock cycles. For example, if the bank

source clock is 625MHz (from APLL1 for example) then one bank source clock cycle is 1.6ns, the smallest phase

adjustment is 0.8ns, and the adjustment range is ±5.6ns. Negative values mean earlier in time (leading) and

positive values mean later in time (lagging). See section 5.6.4.

0000 = 0 bank source clock cycles

1000 = -1.0 bank source clock cycles

0001 = 0.5

1001 = -0.5

0010 = 1.0

1010 = -2.0

0011 = 1.5

1011 = -1.5

0100 = 2.0

1100 = -3.0

0101 = 2.5

1101 = -2.5

0110 = 3.0

1110 = -4.0

0111 = 3.5

1111 = -3.5

OCxSTOP

Output Clock x Start Stop Register

OC1: 20Ah, OC2: 21Ah, OC3: 22Ah, OC4: 23Ah, OC5: 24Ah

OC6: 25Ah, OC7: 26Ah, OC8: 27Ah, OC9: 28Ah, OC10: 29Ah

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

—

SRC[3:0]

NEGLSD

MODE[1:0]

Default

Bits 6 to 3: Output Clock Stop Source (SRC[3:0]). This field specifies the source of the stop signal. See section

5.6.7.

0000 = Never stop

0001 = Logical OR of (the global MCR1.STOP bit) or (the OCx stop bit in the STOPCR registers)

0010 to 0111 = {unused values}

1000 = GPIO0

1001 = GPIO1

1010 = GPIO2

1011 = GPIO3

1100 to 1111 = {unused values}

Bit 2: NEGLSD Stop Behavior (NEGLSD). When an output pair is configured for two different frequencies in

2xCMOS mode (see section 5.6.2) this bit specifies the stop behavior for the pair. This field allows the user to trade

off stop reaction time vs. possible short pulse on the NEG pin.

0 = Stop when higher-speed POS signal has the appropriate edge (see MODE field below)

1 = Stop when lower-speed NEG signal has the appropriate edge.

Setting this bit to 1 guarantees no short high/low time for the POS signal and for the NEG signal, but stopping can

take a long time when the NEG pin is very low frequency, such as 2kHz or even 1Hz.

Setting this bit to 0 allows stopping to happen faster because it depends only on the frequency of the POS signal,

but the NEG signal may have a short high or low time when it stops. For some applications, such as when NEG is

a 1 pulse per second (PPS) signal, a short high or low time when NEG stops may not matter because NEG is

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