ZL30264 datasheet(36/93 Pages) MICROCHIP

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ZL30264-ZL30267

Data Sheet

DS20006555A

6.3

6.3.1

Global Configuration Registers

EESEL

EEPROM Memory Selection Register

00h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

EESEL

—

Default

Bit 7: EEPROM Memory Select (EESEL). This bit is a bank-select that specfies whether device register space or

EEPROM memory is mapped into addresses 0x1 and above. This applies only to the ZL30265 and ZL30267. The

ZL30264 and ZL30266 do not have internal EEPROM memory. Note that ROMSEL has priority over EESEL. See

sections 5.7 and 6.1.4.

0 = Device registers

1= EEPROM memory

MCR1

Master Configuration Register 1

01h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

SRST

HRST

STOP

—

ROSCD

AINCDIS

ODMISO

—

Default

Bit 7: Soft Reset (SRST). This bit resets the entire device except for the microprocessor interface, the SRST bit

itself, the MCR1.HRST bit, the I2CA register, and CFGSR bits 5:0. When SRST is active, the register fields with

pin-programmed defaults do not latch their values from the corresponding input pins. When the SRST bit is

asserted the device

’s auto-configuration boot controller is not started. See section 5.9.

0 = Normal operation

1 = Reset

Bit 6: Hard Reset (HRST). Asserting this bit is functionally equivalent to asserting the RSTN pin. The HRST bit

resets the entire device except for the microprocessor interface and the HRST bit itself. Register fields with pin-

programmed defaults latch their values from the corresponding input pins

, and the device’s auto-configuration boot

controller is started. See section 5.9.

0 = Normal operation

1 = Reset

Bit 5: Output Clock Stop (STOP). Asserting this bit stops all output clocks that are configured with

OCxSTOP.SRC=0001. Note that this signal is ORed with the per-output stop control bit in the STOPCR registers to

make each output’s internal stop control signal. See section 5.6.7.

Bit 3: Ring Oscillator Disable (ROSCD). This bit disables the ring oscillator. It can be set to 1 when auto-

configuration is complete. See section 5.3.4.

0 = Enable

1 = Disable (power-down)

Bit 1: Open Drain MISO Enable (ODMISO). This bit configures the MISO pin to be open-drain. When this bit is

set, the MISO pin only drives low and must have an external pullup resistor.

0 = Disable (MISO drives 0 and 1, high-impedance when not driven)

1 = Enable (MISO drives 0 only, high-impedance all other times)

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