ZL30264 datasheet(40/93 Pages) MICROCHIP

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ZL30264-ZL30267

Data Sheet

DS20006555A

OCMUX2

Output Clock Mux Register 2

08h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

OCMUXF

OCMUXE

OCMUXD

Default

Bits 5 to 4: Output Clock Mux F (OCMUXF[1:0]). Controls the high speed output mux for output group F (OC9

and OC10).

00 = APLL1 Integer divider

01 = APLL1 Fractional divider or bypass path (specified by ACR1.BYPASS)

10 = APLL2 Integer divider

11 = APLL2 Fractional divider or bypass path (specified by A2CR1.BYPASS)

Bits 3 to 2: Output Clock Mux E (OCMUXE[1:0]). Controls the high speed output mux for output group E (OC8).

00 = APLL1 Integer divider

01 = APLL1 Fractional divider or bypass path (specified by ACR1.BYPASS)

10 = APLL2 Integer divider

11 = APLL2 Fractional divider or bypass path (specified by A2CR1.BYPASS)

Bits 1 to 0: Output Clock Mux D (OCMUXD[1:0]). Controls the high speed output mux for output group D (OC6

and OC7).

00 = APLL1 Integer divider

01 = APLL1 Fractional divider or bypass path (specified by ACR1.BYPASS)

10 = APLL2 Integer divider

11 = APLL2 Fractional divider or bypass path (specified by A2CR1.BYPASS)

STOPCR1

Output Clock Stop Control Register 1

09h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

OC8STP

OC7STP

OC6STP

OC5STP

OC4STP

OC3STP

OC2STP

OC1STP

Default

Bit 7: OC8 Stop Control (OC8STP). When SRC=0001 in the OC8STOP register, setting this bit to 1 causes OC8

to stop. Note that this signal is ORed with MCR1

.STOP to make OC8’s internal stop control signal. See section

5.6.7.

Bits 6 to 0: These bits are similar to OC8STP above but for OC7 through OC1.

STOPCR2

Output Clock Stop Control Register 2

0Ah

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

—

OC10STP

OC9STP

Default

Bits 1 to 0: These bits are similar to STOPCR1.OC8STP but for OC10 and OC9.

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