AT45DB021E datasheet(13/74 Pages) DIALOG

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AT45DB021E

DS-AT45DB021E—8789J—03/2021

A low-to-high transition on the CS pin terminates the read operation and tri-state the output pin (SO). The

maximum SCK frequency allowable for the Continuous Array Read is defined by the fCAR1 specification. The

Continuous Array Read bypasses the data buffer and leaves the contents of the Buffer unchanged.

6.3

Continuous Array Read (Low Frequency Mode: 03h Opcode)

This command can be used to read the main memory array sequentially at lower clock frequencies up to maximum

specified by fCAR2. Unlike the previously described read commands, this Continuous Array Read command for

lower clock frequencies does not require the clocking in of dummy bytes after the address byte sequence. To

perform a Continuous Array Read using the standard DataFlash page size (264 bytes), the CS pin must first be

asserted, and then an opcode of 03h must be clocked into the device followed by three address bytes (which

comprise the 24-bit page and byte address sequence). The first 10 bits (PA9 - PA0) of the 19-bit address sequence

specify which page of the main memory array to read, and the last nine bits (BA8 - BA0) of the 19-bit address

sequence specify the starting byte address within the page. To perform a Continuous Array Read using the binary

page size (256 bytes), the opcode 03h must be clocked into the device followed by three address bytes (A17 - A0).

Following the address bytes, additional clock pulses on the SCK pin result in data being output on the SO pin.

The CS pin must remain low during the loading of the opcode, the address bytes, and the reading of data. When

the end of a page in the main memory is reached during a Continuous Array Read, the device continues reading at

the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the

end of one page to the beginning of the next page). When the last bit in the main memory array has been read, the

device continues reading back at the beginning of the first page of memory. As with crossing over page

boundaries, no delays are incurred when wrapping around from the end of the array to the beginning of the array.

A low-to-high transition on the CS pin terminates the read operation and tri-state the output pin (SO). The

maximum SCK frequency allowable for the Continuous Array Read is defined by the fCAR2 specification. The

Continuous Array Read bypasses the data buffer and leaves the contents of the Buffer unchanged.

6.4

Continuous Array Read (Low Power Mode: 01h Opcode)

This command is ideal for applications that want to minimize power consumption and do not need to read the

memory array at high frequencies. Like the 03h opcode, this Continuous Array Read command allows reading the

main memory array sequentially without the need for dummy bytes to be clocked in after the address byte

sequence. The memory can be read at clock frequencies up to maximum specified by fCAR3. To perform a

Continuous Array Read using the standard DataFlash page size (264 bytes), the CS pin must first be asserted, and

then an opcode of 01h must be clocked into the device followed by three address bytes (which comprise the 24-bit

page and byte address sequence). The first 10 bits (PA9 - PA0) of the 19-bit address sequence specify which page

of the main memory array to read and the last nine bits (BA8 - BA0) of the 19-bit address sequence specify the

starting byte address within the page. To perform a Continuous Array Read using the binary page size (256 bytes),

the opcode 01h must be clocked into the device followed by three address bytes (A17 - A0). Following the address

bytes, additional clock pulses on the SCK pin result in data being output on the SO pin.

The CS pin must remain low during the loading of the opcode, the address bytes, and the reading of data. When

the end of a page in the main memory is reached during a Continuous Array Read, the device continues reading at

the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the

end of one page to the beginning of the next page). When the last bit in the main memory array has been read, the

device continues reading back at the beginning of the first page of memory. As with crossing over page

boundaries, no delays are incurred when wrapping around from the end of the array to the beginning of the array.

A low-to-high transition on the CS pin terminates the read operation and tri-state the output pin (SO). The

maximum SCK frequency allowable for the Continuous Array Read is defined by the fCAR3 specification. The

Continuous Array Read bypasses the data buffer and leaves the contents of the Buffer unchanged.

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