33/48

M69KB096AA

Table 16. Synchronous Burst Read AC Characteristics

Note: 1. All the tests are performed with the outputs configured in “Full drive” strength (BCR5=’0’).

2. These timings have been obtained with the AC Measurement Load Circuit shown on Figure 14.. The High-Z timings measure a

3. These timings have been obtained with the AC Measurement Load Circuit shown on Figure 14.. The transition timings measure a

Symbol

Alt.

Parameter

M69KB096AA

Unit

80MHz

66MHz

Min

Max

Min

Max

Burst Access Time

46.5

56

ns

Delay From Clock High to Output Valid

9

11

ns

Address Valid to L High

10

10

ns

Delay From Output Enable Low to Output Valid in Burst mode

20

20

ns

(5)

Chip Enable High between Subsequent Mixed-Mode Read

Operations

55

ns

Chip Enable Low to WAIT Valid

1

7.5

1

7.5

ns

(5)

Maximum Chip Enable Low Pulse

8

8

ns

(4)

Clock Period

12.5

20

15

20

ns

Chip Enable Low to Clock High

4.5

20

5

20

ns

Hold Time From Active Clock Edge

2

2

ns

(2)

Chip Enable High to Output Hi-Z

8

8

ns

Clock Rise Time

Clock Fall Time

1.8

2.0

ns

Clock High to WAIT Valid

Clock High to WAIT Transition

911

ns

Clock High to Output Hi-Z

3

8

3

8

ns

Clock High to Output Transition

2

5

2

5

ns

Output Hold from Clock High

2

2

ns

Clock High to Clock Low

Clock Low to Clock High

45

ns

(2)

Output Enable High to Output Hi-Z

8

8

ns

(3)

Output Enable Low to Output Transition

5

5

ns

Set-up Time to Active Clock Edge

3

3

ns