M69KB096AA

32/48

Figure 22. Continuous Burst Read Showing an Output Delay for End-of-Row Condition (BCR8=0,1)

Note: 1. Non default BCR Register settings: 3 clock cycle latency; WAIT active Low, WAIT asserted during delay; Burst Wrap bit BCR3 set

to ‘0’ (wrap).

3. WAIT will be asserted for a maximum of 2xLC Cycles (LC being the Latency code set through BCR[13-11]).

tKHQV2

tKHQX2

A0-A21

DQ0-DQ15

K

tKHTV

tKHKH

tKLKH

tF

WAIT

WAIT CONFIGIGURED WITH BCR8 = '1'

WAIT CONFIGIGURED WITH BCR8 = '0'

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

AI06787b

E

G

LB/UB

W

DON'T CARE

DON'T CARE

DON'T CARE

DON'T CARE

tKHTX

L

(3)

(4)