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M69KB096AA датащи(PDF) 31 Page - STMicroelectronics |
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M69KB096AA датащи(HTML) 31 Page - STMicroelectronics |
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31 / 48 page ![]() 31/48 M69KB096AA Figure 21. Synchronous Burst Read Suspend and Resume Waveforms Note: 1. Non default BCR Register settings: 3 clock cycle latency; WAIT active Low; WAIT asserted during delay. 2. Clock rates lower than 50MHz (clock period higher than 20ns) are allowed as long as tELKH specifications are met. 0-A21 WAIT 0-D15 tAVKH tKLKL tKHAX tKHQX2 tEHQZ tLLKH tGLQX tEHEL tELKH tWHKH tKHWX tBLKH tKHBX tGHQZ tAVLH tKHKL Hi-Z Valid Output Hi-Z Hi-Z AI08760c W B/UB tKHQV1 L Valid Output Valid Address Valid Address tGLQV tGHQZ Valid Output Valid Output Valid Output Valid Output tKHLH tLLKH tKH tGLQX tGLQV |
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