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M69KB096AA

Figure 5. Synchronous Burst Write Mode (4-word burst)

Note: Non-default BCR Register settings: 3 clock cycle latency; WAIT active Low; Hold Data one clock; WAIT asserted during delay.

Figure 6. Collision Between Refresh and Read Operation

Note: Additional Wait states inserted to allow Refresh completion.

Non-default BCR Register settings: 3 clock cycle latency; WAIT active Low; Hold Data one clock; WAIT asserted during delay.

A0-A21

WAIT

DQ0-DQ15

K

Additional WAIT states inserted

to allow Refresh completion

Address

Valid

AI06776c

L

E

G

W

Hi Z

Hi Z

LB/UB

DQ0

DQ1

DQ2

DQ3

A0-A21

WAIT

DQ0-DQ15

K

Additional WAIT states inserted

to allow Refresh completion

Address

Valid

AI06776b

L

E

G

W

Hi Z

Hi Z

LB/UB

DQ0

DQ1

DQ2

DQ3