INA228 datasheet(21/50 Pages) TI

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Frame 1 Two-Wire Target Address Byte

(1)

Frame 2 Register Pointer Byte

Start By

Controller

ACK By

Target

ACK By

Target

SDA

SCL

R/W

Stop

The value of the Secondary Device Address Byte is determined by the settings of the A0 and A1 pins. Refer to Table 7-2.

Figure 7-9. Typical Register Pointer Set

7.5.1.2 High-Speed I2C Mode

When the bus is idle, both the SDA and SCL lines are pulled high by the pullup resistors. The main device

generates a start condition followed by a valid serial byte containing high-speed (HS) main device code

00001XXX. This transmission is made in fast (400 kHz) or standard (100 kHz) (F/S) mode at no more than

400 kHz. The device does not acknowledge the HS main device code, but does recognize it and switches its

internal filters to support 2.94-MHz operation.

The main device then generates a repeated start condition (a repeated start condition has the same timing

as the start condition). After this repeated start condition, the protocol is the same as F/S mode, except that

transmission speeds up to 2.94 MHz are allowed. Instead of using a stop condition, use repeated start conditions

to maintain the bus in HS-mode. A stop condition ends the HS-mode and switches all the internal filters of the

device to support the F/S mode.

7.5.1.3 SMBus Alert Response

The INA228-Q1 is designed to respond to the SMBus Alert Response address. The SMBus Alert Response

provides a quick fault identification for simple secondary devices. When an Alert occurs, the main device can

broadcast the Alert Response secondary device address (0001 100) with the Read/Write bit set high. Following

this Alert Response, any secondary device that generates an alert identifies itself by acknowledging the Alert

Response and sending its address on the bus.

The Alert Response can activate several different slave devices simultaneously, similar to the I2C General Call.

If more than one slave attempts to respond, bus arbitration rules apply. The losing device does not generate an

Acknowledge and continues to hold the Alert line low until that device wins arbitration.

7.6 Register Maps

7.6.1 INA228-Q1 Registers

Table 7-3 lists the INA228-Q1 registers. All register locations not listed in Table 7-3 should be considered as

reserved locations and the register contents should not be modified.

Table 7-3. INA228-Q1 Registers

Address Acronym

Section

CONFIG

Configuration

ADC_CONFIG

ADC Configuration

SHUNT_CAL

Shunt Calibration

SHUNT_TEMPCO

Shunt Temperature Coefficient

VSHUNT

Shunt Voltage Measurement

VBUS

Bus Voltage Measurement

DIETEMP

Temperature Measurement

CURRENT

Current Result

POWER

Power Result

ENERGY

Energy Result

www.ti.com

INA228-Q1

SLYS022A – JUNE 2020 – REVISED JUNE 2021

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