Writing to a register begins with the first byte transmitted by the main device. This byte is the secondary

device address, with the R/W bit low. The device then acknowledges receipt of a valid address. The next

byte transmitted by the main device is the address of the register to be accessed. This register address value

updates the register pointer to the desired internal device register. The next two bytes are written to the register

addressed by the register pointer. The device acknowledges receipt of each data byte. The main device may

terminate data transfer by generating a start or stop condition.

When reading from the device, the last value stored in the register pointer by a write operation determines which

register is read during a read operation. To change the register pointer for a read operation, a new value must

be written to the register pointer. This write is accomplished by issuing a secondary device address byte with

the R/ W bit low, followed by the register pointer byte. No additional data are required. The main device then

generates a start condition and sends the address byte for the secondary device with the R/W bit high to initiate

the read command. The next byte is transmitted by the secondary device and is the most significant byte of the

register indicated by the register pointer. This byte is followed by an Acknowledge from the main device; then

the secondary device transmits the least significant byte. The main device may or may not acknowledge receipt

of the second data byte. The main device may terminate data transfer by generating a Not-Acknowledge after

receiving any data byte, or generating a start or stop condition. If repeated reads from the same register are

desired, it is not necessary to continually send the register pointer bytes; the device retains the register pointer

value until it is changed by the next write operation.

Figure 7-7 shows the write operation timing diagram. Figure 7-8 shows the read operation timing diagram. These

diagrams are shown for reading/writing to 16 bit registers. Registers with a higher number of bytes will behave

similarly.

Register bytes are sent most-significant byte first, followed by the least significant byte.

Frame 1 Two-Wire Target Address Byte

(1)

Frame 2 Register Pointer Byte

Start By

Controller

ACK By

Target

ACK By

Target

1

9

1

ACK By

Target

1

D15 D14

D13

D12 D11 D10

D9

D8

9

9

SDA

SCL

1

0

0

A3

A2

A1

A0

P7

P6

P5

P4

P3

P2

P1

P0

Frame 4 Data LSByte

Frame 3 Data MSByte

ACK By

Target

Stop By

Controller

1

D7

D6

D5

D4

D3

D2

D1

D0

9

A.

The value of the Secondary Device Address byte is determined by the settings of the A0 and A1 pins. Refer to Table 7-2.

B.

The device does not support packet error checking (PEC) or perform clock stretching.

Figure 7-7. Timing Diagram for Write Word Format

Frame 1 Two-Wire Target Address Byte

(1)

Frame 2 Data MSByte

(2)

1

Start By

Controller

ACK By

Target

ACK By

Controller

From

Target

1

9

1

9

SDA

SCL

0

0

A3

D15 D14 D13

D12

D11 D10

D9

D8

A2

A1

A0

Frame 3 Data LSByte

(2)

Stop

No ACK By

(3)

Controller

From

Target

1

9

D7

D6

D5

D4

D3

D2

D1

D0

A.

The value of the Secondary Device Address byte is determined by the settings of the A0 and A1 pins. Refer to Table 7-2.

B.

Read data is from the last register pointer location. If a new register is desired, the register pointer must be updated. See Figure 7-9.

C.

ACK by the main device can also be sent.

D.

The device does not support packet error checking (PEC) or perform clock stretching.

Figure 7-8. Timing Diagram for Read Word Format

INA228-Q1

SLYS022A – JUNE 2020 – REVISED JUNE 2021

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