INA228 datasheet(18/50 Pages) TI

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• Math overflow — Indicated by the MATHOF bit, reports when an arithmetic operation has caused an internal

• Memory status — Indicated by the MEMSTAT bit, monitors the health of the device non-volatile trim memory.

This bit should always read '1' when the device is operating properly.

• Energy overflow — Indicated by the ENERGYOF bit, reports when the ENERGY register has reached an

overflow state due to data accumulation.

• Charge overflow — Indicated by the CHARGEOF bit, reports when the CHARGE register has reached an

overflow state due to data accumulation.

When the ALERT pin is configured to report the ADC conversion complete event, the ALERT pin becomes a

multipurpose reporting output. Figure 7-6 shows an example where the device reports ADC conversion complete

events while the INA228-Q1 device is subject to shunt over voltage (over current) event, bus under voltage

event, over temperature event and over power-limit event.

Shunt Voltage

Temperature

Bus Voltage

ALERT

(ALATCH = 0)

(APOL = 0)

(CNVR = 1)

Power

Shunt Over Voltage Threshold

Bus Under Voltage Threshold

Over Temp Threshold

Power Over Limit Threshold

BUV

SET

SOV

SET

BUV

CLEAR

SOV

BUV

SET

SOV

CLEAR

BUV

SET

BUV

SET

- No diag. error -

Conversion Complete

Reported

Figure 7-6. Multi-Alert Configuration

7.4 Device Functional Modes

7.4.1 Shutdown Mode

In addition to the two conversion modes (continuous and triggered), the device also has a shutdown mode

(selected by the MODE bits in ADC_CONFIG register) that reduces the quiescent current to less than 5 µA and

turns off current into the device inputs, reducing the impact of supply drain when the device is not being used.

The registers of the device can be written to and read from while the device is in shutdown mode. The device

remains in shutdown mode until another triggered conversion command or continuous conversion command is

received.

The device can be triggered to perform conversions while in shutdown mode. When a conversion is triggered,

the ADC will start conversion; once conversion completes the device will return to the shutdown state.

Note that the shutdown current is specified with an inactive communications bus. Active clock and data activity

will increase the current consumption as a function of the bus frequency as shown in Shutdown IQ vs. Clock

Frequency.

7.4.2 Power-On Reset

Power-on reset (POR) is asserted when VS drops below 1.26V (typical) at which all of the registers are reset to

their default values. A manual device reset can be initiated by setting the RST bit in the CONFIG register. The

default power-up register values are shown in the reset column for each register description. Links to the register

descriptions are shown in Section 7.6.

INA228-Q1

SLYS022A – JUNE 2020 – REVISED JUNE 2021

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