ADA4097-1BUJZ-R5 datasheet(23/27 Pages) AD

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Data Sheet

ADA4097-1

Rev. 0 | Page 23 of 27

POWER DISSIPATION AND THERMAL SHUTDOWN

The ADA4097-1 can drive heavy loads on power supplies up to

±25 V. Therefore, ensure that TJ on the integrated circuit does

not exceed 175°C. The ADA4097-1 is housed in a 6-lead TSOT

package (θJA = 192°C/W).

Junction temperatures exceeding 125°C promote accelerated aging.

Reliability of the ADA4097-1 may be impaired if the junction

temperature exceeds 175°C. If the junction temperature exceeds

175°C, the ADA4097-1 has a final safety measure in the form of

a thermal shutdown that shuts off the output stage and reduces

the internal device currents. When this thermal shutdown function

triggers, the output remains disabled in a high impedance state

until the junction temperature drops 20°C. Persistent heavy loads

and elevated ambient temperatures can cause the ADA4097-1 to

oscillate in and out of thermal shutdown depending on the power

dissipated on the die, until the heavy load is removed (see

Figure 61).

RLOAD = 550Ω

TA = 150°C

SY = ±25V

TJ > 175°C

TJ < 155°C

100ms/DIV

INPUT

10V/DIV

OUTPUT

10V/DIV

Figure 61. ADA4097-1 Cycling In and Out of Thermal Shutdown

It is not recommended to operate near the maximum junction

temperature.

Typically, TJ can be estimated from TA and the device power

dissipation (PD × θJA), as shown in the following equation:

TJ = TA + PD × θJA

The power dissipation in the IC varies as a function of supply

voltage, the output voltage, and load resistance. For a given supply

voltage, the worst case power dissipation (PD(MAX)) in the IC occurs

when the supply current is maximum, and the output voltage is

at half of either supply voltage.

()

(

)

DMAX

s s MAX

PV I









For a given supply voltage, use Figure 62 as a guide for estimating

the minimum load resistance that the ADA4097-1 can drive for

a given supply voltage and a given rise in junction temperature

(ΔTJ). For example, to limit ΔTJ to 50°C, the load driven on the

±15 V supplies (+30 V total supply) must not be lower than

0.8 kΩ. It is assumed that θJA is 192°C/W.

ΔTJ = 50°C

ΔTJ = 75°C

ΔTJ = 100°C

ΔTJ = 125°C

TOTAL SUPPY VOLTAGE (V)

1015202530

3540

4550

0.001

0.01

0.1

Figure 62. Minimum Load Resistance for Given ΔTJ and VSY

CIRCUIT LAYOUT CONSIDERATIONS

Careful and deliberate attention to detail when laying out the

ADA4097-1 boards yields optimal performance. Power supply

bypassing, parasitic capacitance, and component selection all

contribute to the overall performance of the amplifier.

POWER SUPPLY BYPASSING

On single supplies, solder the −VS supply pin directly to a low

impedance ground plane. Bypass the +VS pin to a low impedance

ground plane with a low effective series resistance (ESR) multilayer

ceramic capacitor (MLCC) of 0.1 μF, typically, as close to the ±VS

supply pins as possible. When driving heavy loads, add 10 μF of

supply capacitance. When using split supplies, these conditions

are applicable to the −VS supply pin.

The ADA4097-1 has an internal current source of ~0.6 μA on

the SHDN pin to pull the pin down to −VS and to place the

amplifier in the default amplifying state. If the SHDN state is not

required, hard tie the SHDN pin to the −VS pin. If the SHDN pin is

left floating or driven by a source with significant source impe-

dance (>100 Ω), bypass the −VS supply pin with a small, 1 nF

capacitor to prevent stray signals from coupling on the SHDN pin,

which can inadvertently trigger shutdown.

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