ADA4097-1BUJZ-R5 datasheet(20/27 Pages) AD

20 / 27 page

ADA4097-1

Data Sheet

Rev. 0 | Page 20 of 27

In this case, the noise gain is defined by the following equation:

Noise Gain = 1 + RF/RI

When the amplifier transitions to Over-The-Top operation with

the input common-mode biased near or above the +VS supply,

consider the value of RIN.

The noise gain of the amplifier increases as shown in the

following equation:

OTT

IIN

Noise Gain



 



 



 







where Noise GainOTT is the Over-The-Top noise gain.

The dc closed-loop gain remains mostly unaffected (RF/RI).

However, the loop gain of the amplifier decreases, as expressed

in the following equation:



OTT

Noise Gain

Likewise, the closed-loop bandwidth (BWCLOSED_LOOP) of the

amplifier changes going from normal operation to Over-The-

Top operation.

In normal operation,

BWCLOSED_LOOP ≈



GBP

In Over-The-Top operation,

BWCLOSED_LOOP ≈

OTT

GBP

Noise Gain

Output voltage noise density (eno) is impacted when the device

transitions from normal operation to Over-The-Top operation.

Resistor noise is neglected in both modes of operation in the

following equations.

In normal operation, neglecting resistor noise,









where en is input referred voltage noise density.

In Over-The-Top operation, neglecting resistor noise,

OTT

Noise Gain



OUTPUT

The output of the ADA4097-1 can swing rail-to-rail to within

15 mV of the either supply with no load. The output can source

30 mA and sink 40 mA. The amplifier is internally compensated to

drive at least 200 pF of CLOAD. Adding a series resistance of 50 Ω

between the output and larger capacitive loads extends the

capacitive drive capability of the amplifier.

If the ADA4097-1 enters shutdown, the VOUT pin appears as

high impedance with two steering diodes connected to either

supply. In this state, the output typically leaks <5 nA.

SHUTDOWN PIN (SHDN)

The ADA4097-1 has a dedicated SHDN pin to place the

amplifier in a very low power shutdown state when asserted

high. A logic high is defined by a voltage ≥1.5 V applied to the

SHDN pin with respect to the −VS pin. In shutdown, the amplifier

draws <20 μA of supply current (see Figure 7) and the VOUT pin

is placed in a high impedance state.

The SHDN pin can be driven beyond the +VS supply up to the

absolute maximum voltage (60 V with respect to −VS) and draws

little current (<2.5 μA). For normal active amplifier operation,

the SHDN pin can be floated or driven by an external voltage

source low (within 0.5 V of −VS). If the SHDN pin is left floating,

an internal current source (~600 nA) pulls the SHDN pin to –VS,

which places the amplifier into a default, active amplifying state.

Because of the close proximity of the −IN pin and SHDN pin,

fast edges on the −IN pin may ac-couple to the adjacent high

impedance SHDN pin, inadvertently placing the device in

shutdown. If this scenario is a concern, add a 1 nF capacitor

between the SHDN pin and the −VS pin.

Alternatively, the amplifier can be effectively placed in a low power

state by removing +VS. In this low power state, the inputs typically

leak <1 nA with either ±IN pin biased between −VS and 70 V

above −VS. If the ±IN pins are taken below −VS, they appear as a

diode connected to the −VS supply in series with a resistance of

880 Ω. In this condition, limit the current to <10 mA.

Using an external source to drive the output beyond either ±VS

supply under shutdown conditions may produce unlimited

current and may damage the device.

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