ATMEGA640 datasheet(142/436 Pages) MICROCHIP

142 / 436 page

142

ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (that is, counter reso-

lution). In addition to the counter resolution, the TOP value defines the period time for waveforms generated by the

Waveform Generator.

Figure 17-4 shows a block diagram of the Output Compare unit. The small “n” in the register and bit names indi-

cates the device number (n = n for Timer/Counter n), and the “x” indicates Output Compare unit (A/B/C). The

elements of the block diagram that are not directly a part of the Output Compare unit are gray shaded.

Figure 17-4. Output Compare Unit, Block Diagram

The OCRnx Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For

the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double

buffering synchronizes the update of the OCRnx Compare Register to either TOP or BOTTOM of the counting

sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby

making the output glitch-free.

The OCRnx Register access may seem complex, but this is not case. When the double buffering is enabled, the

CPU has access to the OCRnx Buffer Register, and if double buffering is disabled the CPU will access the OCRnx

directly. The content of the OCR1x (Buffer or Compare) Register is only changed by a write operation (the

Timer/Counter does not update this register automatically as the TCNT1 and ICR1 Register). Therefore OCR1x is

not read via the high byte temporary register (TEMP). However, it is a good practice to read the low byte first as

when accessing other 16-bit registers. Writing the OCRnx Registers must be done via the TEMP Register since the

compare of all 16 bits is done continuously. The high byte (OCRnxH) has to be written first. When the high byte I/O

location is written by the CPU, the TEMP Register will be updated by the value written. Then when the low byte

(OCRnxL) is written to the lower eight bits, the high byte will be copied into the upper 8-bits of either the OCRnx

buffer or OCRnx Compare Register in the same system clock cycle.

For more information of how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 135.

OCFnx (Int.Req.)

= (16-bit Comparator )

OCRnx Buffer (16-bit Register)

OCRnxH Buf. (8-bit)

OCnx

TEMP (8-bit)

DATA BUS (8-bit)

OCRnxL Buf. (8-bit)

TCNTn (16-bit Counter)

TCNTnH (8-bit)

TCNTnL (8-bit)

COMnx1:0

WGMn3:0

OCRnx (16-bit Register)

OCRnxH (8-bit)

OCRnxL (8-bit)

Waveform Generator

TOP

BOTTOM

ATMEGA640 датащи(PDF) 142 Page - Microchip Technology

ATMEGA640 датащи(HTML) 142 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL