ADA4355

Data Sheet

Rev. A | Page 14 of 45

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

A

GND

DNC

VCC

GSEL0 GSEL1

FSEL

DNC

GND

DNC

CS

SCLK

GND

D0AN

D0AP

B

GND

GND

GND

GND

GND

GND

DNC

DNC

GND

GND

SDIO

GND

D1AN

D1AP

C

GND

GND

VCC

VCC

VCC

GND

GND

GND

GND

GND

GND

GND

FCON

FCOP

D

GND

DNC

VCC

VCC

VCC

GND

DNC

NOTES

1. DO NOT CONNECT. THESE BALLS ARE RESERVED.

DNC

DNC

GND

GND

GND

DCON

DCOP

E INPUT

GND

GND

DNC

DNC

GND

GND

DNC

GND

VEA

CLKN

VED

DNC

DNC

F

DNC

DNC

VCC

VCC

VCC

VCC

VLDEN

VCC

GND

DNC

CLKP

VLD

DNC

DNC

ADA4355

TOP VIEW

(BALL SIDE DOWN)

Figure 12. Ball Configuration

Table 8. Ball Configuration and Function Descriptions

Ball No.

Mnemonic

Description

A1, A8, A12, B1 to B6, B9, B10, B12, C1,

C2, C6 to C12, D1, D6, D10 to D12,

E2, E3, E6, E7, E9, F9

GND

P

Ground.

A3, C3 to C5, D3 to D5, F3 to F6, F8

VCC

P

3.3 V Power Supply.

E10

VEA

P

1.8 V Analog Power Supply to ADC.

E12

VED

P

1.8 V Digital Power Supply to ADC.

F12

VLD

PO

1.8 V LDO Output. Connect VLD to VEA and VED to power the ADC

from the internal LDO or leave VLD floating if the ADC is powered from

the external source. Do not connect VLD to the external circuitry.

F7

VLDEN

DI

VLD Output Enable. Set VLDEN = 1 to enable the VLD output.

A6

FSEL

DI

LPF Bandwidth Select. FSEL selects the 100 MHz (FSEL = 0) or 1.0 MHz

(FSEL = 1) LPF bandwidth.

A10

CS

DI

Chip Select. Set CS = 0 to enable SPI mode. CS has an internal 15 kΩ

pull-up resistor.

B11

SDIO

DIO

Serial Data Input/Output. In SPI mode, SDIO is a bidirectional SPI data

input/output with a 31 kΩ internal pull-down resistor.

A11

SCLK

DI

SPI Clock Input in SPI Mode. SCLK has a 30 kΩ internal pull-down resistor.

D13, D14

DCON, DCOP

DO

Data Clock Outputs, Differential.

C13, C14

FCON, FCOP

DO

Frame Clock Outputs, Differential.

B13, B14

D1AN, D1AP

DO

Lane 1 Digital Outputs, Differential.

A13, A14

D0AN, D0AP

DO

Lane 0 Digital Outputs, Differential.

F11, E11

CLKP, CLKN

DI

ADC Sampling Clock Inputs, Differential.

A4, A5

GSEL0, GSEL1

DI

TIA Gain Selection. See Table 9 for the truth table.

E1

INPUT

AI

Analog Input. Connect INPUT to a reversed biased photodiode anode.

A2, A7, A9, B7, B8, D2, D7 to D9, E4, E5,

E8, E13, E14 ,F1, F2, F10, F13, F14

DNC

N/A

Do Not Connect. These balls are reserved.

1

P means power, PO means power output, DI means data input, DIO means data input/output, DO means data output, AI means analog input, and N/A means not applicable.