ADA4355ABCZ datasheet(27/45 Pages) AD

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Data Sheet

ADA4355

Rev. A | Page 27 of 45

APPLICATIONS INFORMATION

POWER AND POWER CONTROL

The 12 mm × 6 mm CSP_BGA has multiple balls designated to

support the ADA4355 power requirements, with 12 balls

assigned to VCC, and one ball each to VEA, VED, and VLD.

Connect VCC to a clean 3.3 V supply to provide power to the

ADA4355 analog core and on-chip LDO. It is important to

connect all VCC balls to the 3.3 V supply. VLD is the on-chip

1.8 V LDO output, and VEA and VED are the ADC supply balls.

To power the ADC via the on-chip LDO, connect VLD to VEA

and VED, and pull VLDEN high (see Figure 3).

If external 1.8 V supplies are desired, disable the on-chip LDO by

pulling VLDEN low and connect VEA and VED to an external

1.8 V supply (see Figure 4).

Ground

The ADA4355 has multiple balls assigned as GND. There is no

connection between the GND balls inside the package.

Therefore, connect all GND balls to a low impedance GND

plane on the PCB.

CLOCKS

For optimum performance, drive the ADC sample clock inputs,

CLKP and CLKN, with a differential signal. The clock signal is

typically ac-coupled into the CLKP and CLKN balls via a

transformer or capacitors. These balls are biased internally

(see Figure 73) and require no external bias.

Clock Input Options

The ADA4355 has a flexible clock input structure. The clock

input can be a CMOS, LVDS, low voltage, positive emitter

coupled logic (LVPECL), or sine wave signal. Regardless of

the type of signal used, clock source jitter is an important

consideration, as described in the Jitter Considerations section.

Figure 79 and Figure 80 show two preferred methods for

clocking the ADA4355 (at clock rates up to 1 GHz prior to the

internal clock divider). A low jitter clock source is converted

from a single-ended signal to a differential signal using either

an RF transformer or an RF balun.

0.1µF

CLOCK

INPUT

50Ω

100Ω

CLKN

CLKP

ADC

Mini-Circuits®

ADT1-1WT, 1:1 Z

XFMR

Figure 79. Transformer-Coupled Differential Clock (Up to 200 MHz)

0.1µF

CLOCK

INPUT

0.1µF

50Ω

CLKN

CLKP

ADC

Figure 80. Balun-Coupled Differential Clock (up to 1 GHz)

The RF balun configuration is recommended for clock

frequencies between 125 MHz and 1 GHz, and the RF

transformer configuration is recommended for clock

frequencies from 10 MHz to 200 MHz.

If a low jitter clock source is not available, another option is to

ac couple a differential PECL signal to the sample clock input

balls, as shown in Figure 81. The AD9510/AD9511/AD9512/

AD9513/AD9514/AD9515/AD9516-0/AD9516-1/AD9516-2/

AD9516-3/AD9516-4/AD9516-5/AD9517-0/AD9517-1/

AD9517-2/AD9517-3/AD9517-4 PECL drivers offer excellent

jitter performance.

0Ω

0.1µF

240Ω

50kΩ

CLKN

CLKP

CLOCK

INPUT

CLOCK

INPUT

ADC

PECL DRIVER

Figure 81. Differential PECL Sample Clock (up to 1 GHz)

A third option is to ac couple a differential LVDS signal to the

sample clock input balls, as shown in Figure 82. The AD9510/

AD9511/AD9512/AD9513/AD9514/AD9515/AD9516-0/

AD9516-1/AD9516-2/AD9516-3/AD9516-4/AD9516-5/

AD9517-0/AD9517-1/AD9517-2/AD9517-3/AD9517-4

LVDS drivers offer excellent jitter performance.

0Ω

0.1µF

50kΩ

CLKN

CLKP

ADC

CLOCK

INPUT

CLOCK

INPUT

LVDS DRIVER

Figure 82. Differential LVDS Sample Clock (up to 1 GHz)

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