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ADA4355ABCZ датащи(PDF) 43 Page - Analog Devices

номер детали ADA4355ABCZ
подробное описание детали  Programmable Transimpedance, Current to Bits Receiver 關Module
PDF  45 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
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ADA4355ABCZ датащи(HTML) 43 Page - Analog Devices

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Data Sheet
ADA4355
Rev. A | Page 43 of 45
Output Phase (Register 0x16)
The power-on default value of this register is 0x03.
Bit 7—Open
Bits[6:4]—Input Clock Phase Adjust
When the clock divider (Register 0x0B) is used, the applied
clock is at a higher frequency than the internal sampling clock.
Bits[6:4] of Register 0x16 determine at which phase the external
clock sampling occurs. The input clock phase adjust is only
applicable when the clock divider is used. Selecting a value for
Bits[6:4] greater than Register 0x0B, Bits[2:0] is prohibited. See
Table 19.
Bits[3:0]—Output Clock Phase Adjust
See Table 20 for details.
Table 19. Input Clock Phase Adjust Options
Input Clock Phase Adjust, Register 0x16, Bits[6:4]
Number of Input Clock Cycles of Phase Delay
000 (Default)
0
001
1
010
2
011
3
100
4
101
5
110
6
111
7
Table 20. Output Clock Phase Adjust Options
Output Clock (DCO), Phase Adjust, Register 0x16, Bits[3:0]
DCOPhaseAdjustment(ApproximateDegreesRelativetotheDxAP/DxANEdge)
0000
0
0001
60
0010
120
0011 (Default)
180
0100
240
0101
300
0110
360
0111
420
1000
480
1001
540
1010
600
1011 through 1111
660



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