ADA4355ABCZ datasheet(42/45 Pages) AD

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ADA4355

Data Sheet

Rev. A | Page 42 of 45

MEMORY MAP REGISTER DESCRIPTIONS

For information on registers not described herein, and for

general information about the functions controlled in

Interfacing to High Speed ADCs via SPI.

Chip ID (Register 0x01)

The power-on default value of this register is 0x8B.

identification and for SPI authentication.

Device Index (Register 0x05)

The power-on default value of this register is 0x33.

Bits[7:6]—Open

Bit 5—Clock Channel DCO

Bit 5 is used to select the output DCO clock channel.

Bit 4—Clock Channel FCO

Bit 4 is used to select the output FCO clock channel.

Bits[3:2]—Open

Bits[1:0]—Data Channel

Setting Bit 1 enables the data channel to receive SPI write

commands. To ensure Bit 0 is configured correctly, perform the

SPI write commands in the ADC SPI Start-Up Sequence

section immediately after start-up or reset.

ADC Power Modes (Register 0x08)

The power-on default value of this register is 0x00.

Bits[7:2]—Open

Bits[1:0]—Power Mode

In normal operation (Bits[1:0] = 00), ADC is active.

In power-down mode (Bits[1:0] = 01), the digital datapath

clocks are disabled, while the digital datapath is reset. Outputs

are disabled.

In standby mode (Bits[1:0] = 10), the digital datapath clocks,

and the outputs are disabled.

During a digital reset (Bits[1:0] = 11), all digital clocks and

outputs (where applicable) on the chip are reset, except the SPI

port. The SPI port is always left under control of the user, that

is, the port is never automatically disabled or in reset, except by

power-on reset.

Clock (Register 0x09)

The power-on default value of this register is 0x00

Bits[7:1]—Open

Bit 0—DCS

This bit turns the DCS on and off.

Clock Divide (Register 0x0B)

The power-on default value of this register is 0x00

Bits[7:3]—Open

Bits[2:0]—Clock Divide Ratio

Bits [2:0] are used to set the clock divide ratio.

Output Mode (Register 0x14)

The power-on default value of this register is 0x01.

Bit 7—Open

Bit 6—LVDS-ANSI/LVDS-IEEE Option

Setting this bit selects the LVDS-IEEE (reduced range) option.

The default setting for this bit is LVDS-ANSI. When LVDS-

ANSI or the LVDS-IEEE reduced range link is selected, the

driver current is automatically selected to give the proper

output swing.

Table 18. LVDS-ANSI/LVDS-IEEE Options

Bit 6

Output Mode

Output Driver Current

LVDS-ANSI (default)

Automatically selected to

give proper swing

LVDS-IEEE reduced range link

Automatically selected to

give proper swing

Bits[5:3]—Open

Bit 2—Output Invert

Setting this bit inverts the output bit stream.

Bit 1—Open

Bit 0—Output Format

By default, this bit is set to send the data output in twos

complement format. Clearing this bit to 0 changes the output

mode to offset binary.

Output Adjust (Register 0x15)

The power-on default value of this register is 0x00.

Bits[7:6]—Open

Bits[5:4]—Output Driver Termination

These bits allow the user to select the internal termination resistor.

Bits[3:1]—Open

Bit 0—Output Driver

Bit 0 of the output adjust register controls the drive strength on

the LVDS driver of the FCO and DCO outputs only. The default

value sets the drive to 1×, or the drive can increase to 2× by setting

the appropriate channel bit in Register 0x05 and then setting Bit 0,

driver termination select. The termination selection takes

precedence over the 2× driver strength on FCO and DCO when

both the output driver termination and output driver are selected.

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