ADA4355ABCZ datasheet(31/45 Pages) AD

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Data Sheet

ADA4355

Rev. A | Page 31 of 45

Figure 90 shows a TIE jitter histogram with trace lengths

greater than 24 inches on standard FR-4 material.

10k

12k

–800

–600

–400

–200

200

400

600

TIME (ps)

Figure 90. TIE Jitter Histogram for Trace Lengths Greater Than 24 Inches

(Approximate 36 Inch Trace Length Result Shown) on Standard FR-4 Material

Two output clocks assist in capturing data from the ADA4355.

The DCO clocks the output data and is equal to 4× the sample

clock (CLK) rate for the default mode of operation. Data is clocked

out of the ADA4355 and must be captured on the rising and falling

edges of the DCO that supports DDR capturing. The FCO signals

the start of a new output byte and is equal to the sample clock

rate in 1× frame mode. See Figure 6 for more information.

When the SPI is used, the DCO phase can be adjusted in

approximately 60° increments relative to one data cycle (30°

relative to one DCO cycle). This adjustment allows the user to

refine system time margins, if required. The example DCOP

and DCON timing, as shown in Figure 6, is 180° relative to one

data cycle (90° relative to one DCO cycle).

In power-on default mode, as shown in Figure 6, the MSB is

first in the data output serial stream. This configuration can be

inverted by programming the SPI so that the LSB is first in the

data output serial stream.

Digital Output Coding

There are 12 digital output test pattern options available that

can be initiated through the SPI. This feature is useful when

validating receiver capture and timing. Refer to Table 13 for

the output bit sequencing options available. Some test patterns

have two serial sequential words and can be alternated in

various ways depending on the test pattern chosen.

Note that some patterns do not adhere to the data format select

option. In addition, custom, user defined test patterns can be

assigned in the following register addresses: Register 0x19,

Table 12. Digital Output Coding

Input (V)1

Condition

Offset Binary Output Mode

Twos Complement Mode

VIN+ − VIN−

<−1 V − 0.5 LSB

0000 0000 0000 0000

1000 0000 0000 0000

VIN+ − VIN−

−1 V

0000 0000 0000 0000

1000 0000 0000 0000

VIN+ − VIN−

0 V

1000 0000 0000 0000

0000 0000 0000 0000

VIN+ − VIN−

+1 V − 1.0 LSB

1111 1111 1111 1100

0111 1111 1111 1100

VIN+ − VIN−

>+1 V − 0.5 LSB

1111 1111 1111 1100

0111 1111 1111 1100

VIN+ and VIN− are the positive and negative input voltages.

Table 13. Flexible Output Test Modes

Output Test

Mode Bit

Sequence

Pattern Name

Digital Output Word 1

Digital Output Word 2

Subject to

Data Format

Select

Notes

0000

Off (default)

Not applicable (N/A)

Not applicable

Not

applicable

0001

Midscale short

1000 0000 0000 (12-bit)

1000 0000 0000 0000 (16-bit)

Not applicable

Yes

Offset binary

code shown

0010

+Full-scale short

1111 1111 1111 (12-bit)

1111 1111 1111 1100 (16-bit)

Not applicable

Yes

Offset binary

code shown

0011

−Full-scale short

0000 0000 0000 (12-bit)

0000 0000 0000 0000 (16-bit)

Not applicable

Yes

Offset binary

code shown

0100

Checkerboard

1010 1010 1010 (12-bit)

1010 1010 1010 1000 (16-bit)

0101 0101 0101 (12-bit)

0101 0101 0101 0100 (16-bit)

Not

applicable

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