ADA4355ABCZ datasheet(28/45 Pages) AD

28 / 45 page

ADA4355

Data Sheet

Rev. A | Page 28 of 45

In some applications, it may be acceptable to drive the sample

clock inputs with a single-ended 1.8 V CMOS signal. In such

applications, drive the CLKP ball directly from a CMOS gate,

and bypass the CLKN ball to ground with a 0.1 µF capacitor

(see Figure 83).

OPTIONAL

100Ω

0.1µF

50Ω1

50Ω RESISTOR IS OPTIONAL.

CLKN

CLKP

ADC

VCC

1kΩ

CLOCK

INPUT

CMOS DRIVER

Figure 83. Single-Ended 1.8 V CMOS Input Clock (up to 200 MHz)

Input Clock Divider

The ADA4355 contains an input clock divider that can divide

the input clock by integer values from 1 to 8. The power-on

default, clock divider ratio is always 1. If a different clock divide

ratio is required, change SPI Register 0x0B. To achieve a given

sample rate, multiply the frequency of the externally applied

clock by the divide value. The increased rate of the external

clock normally results in lower clock jitter, which is beneficial

for intermediate frequency (IF) undersampling applications.

Clock Duty Cycle

The ADC uses both clock edges to generate a variety of internal

timing signals and, as a result, can be sensitive to the clock duty

cycle. Commonly, a ±5% tolerance is required on the clock duty

cycle to maintain dynamic performance characteristics.

The ADA4355 offers a duty cycle stabilizer (DCS) that retimes

the nonsampling (falling) edge, providing an internal clock

signal with a nominal 50% duty cycle. The DCS allows the user

to provide a wide range of clock input duty cycles without

affecting the performance of the ADA4355. Noise and distortion

performance are nearly unchanged for a wide range of duty cycles

with the DCS on. To bypass DCS, the user can change SPI

Jitter in the rising edge of the clock is still a concern and is not

easily reduced by the internal stabilization circuit. The duty

cycle control loop does not function for clock rates <20 MHz,

nominally. The loop has a time constant associated with it that

must be considered in applications where the clock rate can

change dynamically. A wait time of 5 µs is required after a

dynamic clock frequency increase or decrease before the DCS

loop relocks to the input signal.

Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality of

the clock input. The following equation shows how signal-to-

noise ratio (SNR) degrades at a given input frequency (fA) due

only to aperture jitter (tJ):

SNR Degradation = 20 log10













A t

In this equation, the rms aperture jitter represents the rms of all

jitter sources, including the clock input, analog input signal,

and ADC aperture jitter specifications. IF undersampling

applications are particularly sensitive to jitter. The effect of

jitter alone on SNR, with no other noise contributors, is shown

in Figure 84.

100

ANALOG INPUT FREQUENCY (MHz)

1000

16 BITS

14 BITS

12 BITS

100

110

120

130

0.125ps

0.25ps

0.5ps

1.0ps

2.0ps

10 BITS

8 BITS

RMS CLOCK JITTER REQUIREMENT

Figure 84. Ideal SNR vs. Analog Input Frequency and Jitter

Treat the clock input as an analog signal when aperture jitter

can affect the dynamic range of the ADA4355. Separate clock

driver power supplies from the ADC output driver supplies to

avoid modulating the clock signal with digital noise. Low jitter,

crystal oscillators are the best clock sources. If the clock is

generated from another type of source (by gating, dividing, or

other methods), it is recommended to retime the clock by the

original clock as the last step.

See the AN-501 Application Note and the AN-756 Application

Note for more information about jitter performance as it relates

to the internal ADC of the ADA4355.

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