STM32G031F6 datasheet(29/117 Pages) STMICROELECTRONICS

29 / 117 page

DS12992 Rev 2

29/117

STM32G031x4/x6/x8

Functional overview

Features of the I2C peripheral:

•

I2C-bus specification and user manual rev. 5 compatibility:

–

Slave and master modes, multimaster capability

–

Standard-mode (Sm), with a bitrate up to 100 kbit/s

–

Fast-mode (Fm), with a bitrate up to 400 kbit/s

–

Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and extra output drive I/Os

–

7-bit and 10-bit addressing mode, multiple 7-bit slave addresses

–

Programmable setup and hold times

–

Clock stretching

•

SMBus specification rev 3.0 compatibility:

–

Hardware PEC (packet error checking) generation and verification with ACK

control

–

Command and data acknowledge control

–

Address resolution protocol (ARP) support

–

Host and Device support

–

SMBus alert

–

Timeouts and idle condition detection

•

PMBus rev 1.3 standard compatibility

•

Independent clock: a choice of independent clock sources allowing the I2C

communication speed to be independent of the PCLK reprogramming

•

Wakeup from Stop mode on address match

•

Programmable analog and digital noise filters

•

1-byte buffer with DMA capability

3.19

Universal synchronous/asynchronous receiver transmitter

(USART)

The device embeds universal synchronous/asynchronous receivers/transmitters (USART1,

USART2) that communicate at speeds of up to 8 Mbit/s.

They provide hardware management of the CTS, RTS and RS485 DE signals,

multiprocessor communication mode, master synchronous communication and single-wire

Table 8. I2C implementation

I2C features(1)

1. X: supported

I2C1

I2C2

Standard mode (up to 100 kbit/s)

Fast mode (up to 400 kbit/s)

Fast Mode Plus (up to 1 Mbit/s) with extra output drive I/Os

Programmable analog and digital noise filters

SMBus/PMBus hardware support

Independent clock

Wakeup from Stop mode on address match

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