STM32G031F6 datasheet(17/117 Pages) STMICROELECTRONICS

17 / 117 page

DS12992 Rev 2

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STM32G031x4/x6/x8

Functional overview

3.7.2

Power supply supervisor

The device has an integrated power-on/power-down (POR/PDR) reset active in all power

modes except Shutdown and ensuring proper operation upon power-on and power-down. It

maintains the device in reset when the supply voltage is below VPOR/PDR threshold, without

the need for an external reset circuit. Brownout reset (BOR) function allows extra flexibility. It

can be enabled and configured through option bytes, by selecting one of four thresholds for

rising VDD and other four for falling VDD.

The device also features an embedded programmable voltage detector (PVD) that monitors

the VDD power supply and compares it to VPVD threshold. It allows generating an interrupt

when VDD level crosses the VPVD threshold, selectively while falling, while rising, or while

falling and rising. The interrupt service routine can then generate a warning message and/or

put the MCU into a safe state. The PVD is enabled by software.

3.7.3

Voltage regulator

Two embedded linear voltage regulators, main regulator (MR) and low-power regulator

(LPR), supply most of digital circuitry in the device.

The MR is used in Run and Sleep modes. The LPR is used in Low-power run, Low-power

sleep and Stop modes.

In Standby and Shutdown modes, both regulators are powered down and their outputs set in

high-impedance state, such as to bring their current consumption close to zero. However,

SRAM data retention is possible in Standby mode, in which case the LPR remains active

and it only supplies the SRAM.

3.7.4

Low-power modes

By default, the microcontroller is in Run mode after system or power reset. It is up to the

user to select one of the low-power modes described below:

•

Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

•

Low-power run mode

This mode is achieved with VCORE supplied by the low-power regulator to minimize the

regulator's operating current. The code can be executed from SRAM or from Flash,

and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can

be clocked by HSI16.

•

Low-power sleep mode

This mode is entered from the low-power run mode. Only the CPU clock is stopped.

When wakeup is triggered by an event or an interrupt, the system reverts to the Low-

power run mode.

•

Stop 0 and Stop 1 modes

In Stop 0 and Stop 1 modes, the device achieves the lowest power consumption while

retaining the SRAM and register contents. All clocks in the VCORE domain are stopped.

The PLL, as well as the HSI16 RC oscillator and the HSE crystal oscillator are

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