STM32G031F6 datasheet(18/117 Pages) STMICROELECTRONICS

18 / 117 page

Functional overview

STM32G031x4/x6/x8

18/117

DS12992 Rev 2

disabled. The LSE or LSI keep running. The RTC can remain active (Stop mode with

RTC, Stop mode without RTC).

Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode,

so as to get clock for processing the wakeup event. The main regulator remains active

in Stop 0 mode while it is turned off in Stop 1 mode.

•

Standby mode

The Standby mode is used to achieve the lowest power consumption, with POR/PDR

always active in this mode. The main regulator is switched off to power down VCORE

domain. The low-power regulator is either switched off or kept active. In the latter case,

it only supplies SRAM to ensure data retention. The PLL, as well as the HSI16 RC

oscillator and the HSE crystal oscillator are also powered down. The RTC can remain

active (Standby mode with RTC, Standby mode without RTC).

For each I/O, the software can determine whether a pull-up, a pull-down or no resistor

shall be applied to that I/O during Standby mode.

Upon entering Standby mode, register contents are lost except for registers in the RTC

domain and standby circuitry. The SRAM contents can be retained through register

setting.

The device exits Standby mode upon external reset event (NRST pin), IWDG reset

event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event

(alarm, periodic wakeup, timestamp, tamper), or when a failure is detected on LSE

(CSS on LSE).

•

Shutdown mode

The Shutdown mode allows to achieve the lowest power consumption. The internal

regulator is switched off to power down the VCORE domain. The PLL, as well as the

HSI16 and LSI RC-oscillators and HSE crystal oscillator are also powered down. The

RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).

The BOR is not available in Shutdown mode. No power voltage monitoring is possible

in this mode. Therefore, switching to RTC domain is not supported.

SRAM and register contents are lost except for registers in the RTC domain.

The device exits Shutdown mode upon external reset event (NRST pin), IWDG reset

event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event

(alarm, periodic wakeup, timestamp, tamper).

3.7.5

Reset mode

During and upon exiting reset, the schmitt triggers of I/Os are disabled so as to reduce

power consumption. In addition, when the reset source is internal, the built-in pull-up

resistor on NRST pin is deactivated.

3.7.6

VBAT operation

The VBAT power domain, consuming very little energy, includes RTC, and LSE oscillator and

backup registers.

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