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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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W6100 датащи(PDF) 39 Page - WIZnet Co., Ltd |
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W6100 датащи(HTML) 39 Page - WIZnet Co., Ltd |
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39 / 149 page  W6100 – Hardwired Dual TCP/IP Stack Controller 39/149 4.1.24 PHYCR0 (PHY Control Register 0) [WO] [0x301C] [0x00] PHYCR0 sets Ethernet PHY operation mode when SYSR[PHYL] = ‘0’((PHYLCKR(PHY Lock Register) is Unlock). Bits set by PHYCR0 can be checked to PHYSR [5:3]. 7 6 5 4 3 2 1 0 - - - - - MODE2 MODE1 MODE0 WO WO WO Bit Symbol Description [7:3] - Reserved [2:0] MODE MODE2 MODE1 MODE0 Description 0 x x Auto Negotiation 1 0 0 100BASE-TX FDX 1 0 1 100BASE-TX HDX 1 1 0 10BASE-TX FDX 1 1 1 10BASE-TX HDX 4.1.25 PHYCR1 (PHY Control Register 1) [R=W] [0x301D] [0x40] PHYCR1 sets PHY power down Mode and PHY HW Reset when SYSR[PHYL] = ‘0’((PHYLCKR(PHY Lock Register) is Unlock). 7 6 5 4 3 2 1 0 - - PWDN - TE - - RST - - R=W - R=W - - AC Bit Symbol Description 7 - Reserved 6 - Should be always written by ‘1’ 5 PWDN PHY Power Down 0 : Disable Power Down Mode SYS_CLK is changed according to SYCR1[CLKSEL]. SYCR1[CLKSEL] SYS_CLK 0 100 MHz 1 25 MHz |
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