W6100 datasheet(7/149 Pages) WIZNET

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W6100 – Hardwired Dual TCP/IP Stack Controller

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4.2.2 Sn_PSR (SOCKET n Prefer Source IPv6 Address Register)..........................57

4.2.3 Sn_CR (SOCKET n Command Register) ...............................................57

4.2.4 Sn_IR (SOCKET n Interrupt Register) .................................................60

4.2.5 Sn_IMR (SOCKET n Interrupt Mask Register).........................................60

4.2.6 Sn_IRCLR (Sn_IR Clear Register) ......................................................61

4.2.7 Sn_SR (SOCKET n Status Register) ....................................................61

4.2.8 Sn_ESR (SOCKET n Extension Status Register) ......................................62

4.2.9 Sn_PNR (SOCKET n IP Protocol Number Register) ..................................63

4.2.10 Sn_TOSR (SOCKET n IP Type of Service Register) .................................63

4.2.11 Sn_TTLR (SOCKET n IP Time To Live Register) ....................................63

4.2.12 Sn_FRGR (SOCKET n Fragment Offset in IP Header Register) ...................63

4.2.13 Sn_MSSR (SOCKET n Maximum Segment Size Register)...........................64

4.2.14 Sn_PORTR (SOCKET n Source Port Register) .......................................64

4.2.15 Sn_DHAR (SOCKET n Destination Hardware Address Register) ..................65

4.2.16 Sn_DIPR (SOCKET n Destination IPv4 Address Register) ..........................65

4.2.17 Sn_DIP6R (SOCKET n Destination IPv6 Address Register) ........................65

4.2.18 Sn_DPORTR (SOCKET n Destination Port Register)................................66

4.2.19 Sn_MR2 (SOCKET n Mode register 2) ................................................67

4.2.20 Sn_RTR (SOCKET n Retransmission Time Register) ...............................68

4.2.21 Sn_RCR (SOCKET n Retransmission Count Register) ..............................68

4.2.22 Sn_KPALVTR (SOCKET n Keep Alive Time Register)...............................68

4.2.23 Sn_TX_BSR (SOCKET n TX Buffer Size Register) ...................................68

4.2.24 Sn_TX_FSR (SOCKET n TX Free Buffer Size Register) .............................69

4.2.25 Sn_TX_RD (SOCKET n TX Read Pointer Register) ..................................69

4.2.26 Sn_TX_WR (SOCKET n TX Write Pointer Register) ................................70

4.2.27 Sn_RX_BSR (SOCKET n RX Buffer Size Register) ...................................70

4.2.28 Sn_RX_RSR (SOCKET n RX Received Size Register)................................70

4.2.29 Sn_RX_RD (SOCKET n RX Read Pointer Register) ..................................71

4.2.30 Sn_RX_WR (SOCKET n RX Write Pointer Register) ................................71

5. HOST Interface Mode .............................................................................. 72

5.1

SPI Mode ...................................................................................72

5.1.1 SPI Frame ................................................................................73

5.1.2 Variable Length Data Mode (VDM) ....................................................76

5.1.3 Fixed Length Data Mode (FDM)........................................................77

5.2

Parallel BUS Mode ........................................................................80

5.2.1 Parallel BUS Data Write ................................................................81

5.2.2 Parallel BUS Data Read.................................................................82

6. Functional Description ............................................................................ 83

6.1

Initialization ..............................................................................83

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