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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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W6100 датащи(PDF) 30 Page - WIZnet Co., Ltd |
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W6100 датащи(HTML) 30 Page - WIZnet Co., Ltd |
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30 / 149 page  W6100 – Hardwired Dual TCP/IP Stack Controller 30/149 4.1.5 SYCR1 (System Config Register 1) [R=W][0x2005] [0x80] Interrupt enable and system operation clock (SYS_CLK) can be set by this register. 7 6 5 4 3 2 1 0 IEN - - - - - - CLKSEL R=W R=W Bit Symbol Description 7 IEN Interrupt Enable It makes Interrupt enable. 0 : Disable – INTn is always High. 1 : Enable – When the event occurs, INTn goes low. [6:1] - Reserved 0 CLKSEL System Operation Clock Select In case of SYSR[CHPL] = ‘0’, Select SYS_CLK. 0 : 100MHz 1 : 25MHz 4.1.6 TCNTR (Tick Counter Register) [RO][0x2016-0x2017][0x0000] It is automatically increased every 100us. 4.1.7 TCNTRCLR (TCNTR Clear Register) [WO][0x2020][0x00] With Write operation to TCNTCLR, TCNTR counter value is initialized. 4.1.8 IR (Interrupt Register) [RO] [0x2100] [0x00] When an event such as WOL (Wake On LAN) or destination unreachable occurs, the corresponding bit of IR is set to 1. 7 6 5 4 3 2 1 0 WOL UNR6 IPCONF UNR4 PTERM RO RO RO RO RO |
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