CS47L24 datasheet(97/256 Pages) CIRRUS

97 / 256 page

CS47L24

Rev 4.1

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R4608

(1200h)

DSP2

Control 1

DSP2_MEM_EN

DSP2 Memory Control

0 = DSP2 memory is cleared when

DSP2_SYS_ENA=0, and during Hardware

Reset or Software Reset.

1 = DSP2 memory is retained when

DSP2_SYS_ENA=0. DSP2 memory is

retained during Hardware Reset and

Software Reset.

DSP2_SYS_ENA

DSP2 Clock Enable

0 = Disabled

1 = Enabled

The DSP2 Clock must be enabled for

DSP2 firmware register access, code

execution, or DMA operation.

The DSP2 Core must be reset (by writing

DSP2_CORE_ENA=0) when disabling the

DSP2 Clock.

R4609

(1201h)

DSP2

Clocking 1

2:0

DSP2_CLK_SEL

[2:0]

000

DSP2 Clock Frequency Select

000 = 6.144MHz (5.6448MHz)

001 = 12.288MHz (11.2896MHz)

010 = 24.576MHz (22.5792MHz)

011 = 49.152MHz (45.1584MHz)

100 = 73.728MHz (67.7376MHz)

101 = 98.304MHz (90.3168MHz)

110 = 147.456MHz (135.4752MHz)

111 = Reserved

The DSP2 Clock must be less than or

equal to the SYSCLK frequency. The

frequencies must also be integer-related

(e.g., divide by 1, 2, 3 etc.).

The frequencies in brackets apply for

44.1kHz-related sample rates only (i.e.,

SAMPLE_RATE_n = 01XXX).

R4612

(1204h)

DSP2

Status 1

DSP2_RAM_RD

DSP2 Memory Status

0 = Not ready

1 = Ready

Note - DSP2 memory should not be

accessed until this bit has been set.

R4614

(1206h)

DSP2

Status 3

3:1

DSP2_CLK_SEL

_STS [2:0

000

DSP2 Clock Frequency

(Read only, Only valid when the

respective DSP Clock is enabled)

000 = 6.144MHz (5.6448MHz)

001 = 12.288MHz (11.2896MHz)

010 = 24.576MHz (22.5792MHz)

011 = 49.152MHz (45.1584MHz)

100 = 73.728MHz (67.7376MHz)

101 = 98.304MHz (90.3168MHz)

110 = 147.456MHz (135.4752MHz)

111 = Reserved

The frequencies in brackets apply for

44.1kHz-related sample rates only (i.e.,

SAMPLE_RATE_n = 01XXX).

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