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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CS47L24 датащи(PDF) 90 Page - Cirrus Logic |
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CS47L24 датащи(HTML) 90 Page - Cirrus Logic |
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90 / 256 page  CS47L24 90 Rev 4.1 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R3824 (0EF0h) ISRC 1 CTRL 1 14:11 ISRC1_FSH [3:0] 0000 ISRC1 High Sample Rate (Sets the higher of the ISRC1 sample rates) 0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 8kHz to 192kHz. The ISRC1_FSH and ISRC1_FSL fields must both select sample rates referenced to the same clock domain (SYSCLK or ASYNCCLK). All ISRC1_DECn_SRC registers should be set to 00h before changing ISRC1_FSH. R3825 (0EF1h) ISRC 1 CTRL 2 14:11 ISRC1_FSL [3:0] 0000 ISRC1 Low Sample Rate (Sets the lower of the ISRC1 sample rates) 0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 8kHz to 192kHz. The ISRC1_FSH and ISRC1_FSL fields must both select sample rates referenced to the same clock domain (SYSCLK or ASYNCCLK). All ISRC1_INTn_SRC registers should be set to 00h before changing ISRC1_FSL. R3826 (0EF2h) ISRC 1 CTRL 3 15 ISRC1_INT1_EN A 0 ISRC1 INT1 Enable (Interpolation Channel 1 path from ISRC1_FSL rate to ISRC1_FSH rate) 0 = Disabled 1 = Enabled 14 ISRC1_INT2_EN A 0 ISRC1 INT2 Enable (Interpolation Channel 2 path from ISRC1_FSL rate to ISRC1_FSH rate) 0 = Disabled 1 = Enabled 13 ISRC1_INT3_EN A 0 ISRC1 INT3 Enable (Interpolation Channel 3 path from ISRC1_FSL rate to ISRC1_FSH rate) 0 = Disabled 1 = Enabled 12 ISRC1_INT4_EN A 0 ISRC1 INT4 Enable (Interpolation Channel 4 path from ISRC1_FSL rate to ISRC1_FSH rate) 0 = Disabled 1 = Enabled 9 ISRC1_DEC1_EN A 0 ISRC1 DEC1 Enable (Decimation Channel 1 path from ISRC1_FSH rate to ISRC1_FSL rate) 0 = Disabled 1 = Enabled |
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