поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

Preview PDF HTML

CS61880 датащи(PDF) 58 Page - Cirrus Logic

номер детали CS61880
подробное описание детали  OCTAL E1 LINE INTERFACE UNIT
PDF  70 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  CIRRUS [Cirrus Logic]
домашняя страница  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS61880 датащи(HTML) 58 Page - Cirrus Logic

Back Button CS61880 Datasheet HTML 54Page - Cirrus Logic CS61880 Datasheet HTML 55Page - Cirrus Logic CS61880 Datasheet HTML 56Page - Cirrus Logic CS61880 Datasheet HTML 57Page - Cirrus Logic CS61880 Datasheet HTML 58Page - Cirrus Logic CS61880 Datasheet HTML 59Page - Cirrus Logic CS61880 Datasheet HTML 60Page - Cirrus Logic CS61880 Datasheet HTML 61Page - Cirrus Logic CS61880 Datasheet HTML 62Page - Cirrus Logic Next Button
Zoom Inzoom in Zoom Outzoom out
 58 / 70 page
background image
CS61880
58
DS450PP3
19.7 Master Clock Switching Characteristics
19.8 Transmit Switching Characteristics
19.9 Receive Switching Characteristics
Notes: 19. Output load capacitance = 50 pF.
20. MCLK is not active.
Parameter
Symbol
Min.
Typ
Max
Units
MASTER CLOCK (MCLK)
Master Clock Frequency
MCLK
2.048
MHz
Master Clock Tolerance
-
-100
+100
ppm
Master Clock Duty Cycle
-
40
50
60
%
Parameter
Symbol
Min.
Typ
Max
Units
TCLK Frequency
1/tpw2
-
2.048
-
MHz
TPOS/TNEG Pulse Width (RZ Mode)
236
244
252
ns
TCLK Tolerance (NRZ Mode)
-50
-
50
PPM
TCLK Duty Cycle
tpwh2/tpw2
--
90
%
TCLK Pulse Width
20
-
-
ns
TCLK Burst Rate
Note 10
--
20
MHz
TPOS/TNEG to TCLK Falling Setup Time (NRZ Mode)
tsu2
25
-
-
ns
TCLK Falling to TPOS/TNEG Hold time (NRZ Mode)
th2
25
-
-
ns
TXOE Asserted Low to TX Driver HIGH-Z
-
-
1
µs
TCLK Held Low to Driver HIGH-Z
Note 20
812
20
µs
Parameter
Symbol
Min.
Typ
Max
Units
RCLK Duty Cycle
Note 10
40
50
60
%
RCLK Pulse Width
Note 10
196
244
328
ns
RPOS/RNEG Pulse Width (RZ Mode)
Note 10
200
244
300
ns
RPOS/RNEG to RCLK rising setup time
Note 10
tsu
200
244
ns
RPOS/RNEG to RCLK hold time
Note 10
th
200
244
ns
RPOS/RNEG Output to RCLK Output (RZ Mode)
Note 10
-
-
10
ns
Rise/Fall Time, RPOS, RNEG, RCLK, LOS outputs
Note 19
tr, tf
-
-
85
ns



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com