TMS29F010

131072 BY 8-BIT

FLASH MEMORY

SMJS840A – NOVEMBER 1997 – REVISED JUNE 1998

9

POST OFFICE BOX 1443

operation status

status bit definitions

During operation of the embedded program and erase functions, the status of the device can be determined

by reading the data state of designated outputs. The data-polling bit (DQ7) and toggle-bit (DQ6) require multiple

successive reads to observe a change in the state of the designated output. Table 4 defines the values of the

status flags.

Device Operation‡

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

Byte-programming in progress

DQ7

T

0

X

0

X

X

X

Byte-programming exceed time limit

DQ7

T

1

X

0

X

X

X

Byte-programming complete

D

D

D

D

D

D

D

D

Sector / chip-erase in progress

0

T

0

X

1

X

X

X

Sector / chip-erase exceed time limit

0

T

1

X

1

X

X

X

Sector / chip-erase complete

1

1

1

1

1

1

1

1

† T= toggle, D = data, X = data undefined, DQ7 = complement of data written to DQ7

‡ DQ4, DQ2, DQ1, DQ0 are reserved for future use.

data-polling (DQ7)

The data-polling status function outputs the complement of the data latched into the DQ7 data register while

the write-state machine (WSM) is engaged in a program or erase operation. Data bit DQ7 changes from

complement to true to indicate the end of an operation. Data polling is available only during the

byte-programming, chip-erase, sector-erase, and sector-erase timing delay. Data polling is valid after the rising

edge of W in the last bus cycle of the command sequence loaded into the command register. Figure 10 shows

a flow chart of the data-polling operation.

During a byte-program operation, reading DQ7 outputs the complement of the DQ7 data to be programmed at

the selected address location. Upon completion, reading DQ7 outputs the true DQ7 data loaded into the

program data register. During erase operations, reading DQ7 outputs a logic 0, and upon completion, reading

DQ7 outputs a logic 1. Also, data polling must be performed at a sector address that is within a sector being

erased; otherwise, the status is not valid. When using data polling, the address must remain stable throughout

the operation.

During a data-polling read, while G is low, DQ7 can change asynchronously with the other DQs. Depending on

the read timing, the system can read valid data on DQ7, while other DQ pins are still invalid. The data on

DQ0–DQ7 is valid with a subsequent read of the device. See Figure 11 for the data-polling timing diagram.

toggle-bit (DQ6)

The toggle-bit status function outputs data on DQ6 that toggles between logic 1 and logic 0 while the WSM is

engaged in a program or erase operation. When toggle-bit DQ6 stops toggling after two consecutive reads to

the same address, the operation is complete. The toggle bit is available only during the byte-programming,

chip-erase, sector-erase, and sector-erase timing delay. Toggle bit data is valid after the rising edge of W in the

last bus cycle of the command sequence loaded into the command register. Figure 12 shows a flow chart for

the toggle-bit status-read algorithm. Depending on the read timing, DQ6 can stop toggling while other DQ pins

are still invalid. The data on DQ0–DQ7 is valid with a subsequent read of the device. Figure 13 shows the

toggle-bit timing diagram.