TMS29F010

131072 BY 8-BIT

FLASH MEMORY

SMJS840A – NOVEMBER 1997 – REVISED JUNE 1998

6

POST OFFICE BOX 1443

algorithm-selection mode

The algorithm-selection mode provides access to a binary code that matches the device with its proper

on address pin A9. Address pin A1 must be logic-low. Two bytes of code are accessed by toggling address pin

available to be placed on address pin A9. Table 2 shows the binary algorithm-selection codes for the

TMS29F010.

ALGORITHM SELECTION

A0

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

HEX

Byte 0

0

0

0

0

0

0

0

0

1

01h

Byte 1

1

0

0

1

0

0

0

0

0

20h

† A1 = VIL, E = G = VIL

erasure and programming

Erasure and programming of the TMS29F010 are accomplished by writing a sequence of commands using

standard microprocessor-write timings. The commands are written to a command register and input to the

command-state machine (CSM). The CSM interprets the command entered and initiates program and erase

operations as instructed. The CSM acts as the interface between the write-state machine (WSM) and the

external chip operations. The WSM controls all voltage generation, pulse generation, preconditioning, and

verification of the memory contents. Program and sector/chip-erase functions are fully automatic. Once the end

If a byte-program or chip-erase operation is in progress, additional program/erase commands are ignored until

the operation ends.

command definitions

Device operating modes are selected by writing specific address and data sequences into the command

register. Table 3 defines the valid command sequences. Writing incorrect address and data values or writing

them in the incorrect sequence causes the device to reset to the read mode. The command register does not

occupy an addressable memory location. The register stores the command sequence, along with the address

for a more complete description.