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Am79Q02/021/031 Data Sheet
26, 27. Write/Read Interrupt Mask Register
MPI Command
(6C/6Dh)
R/W = 0: Write
R/W = 1: Read
Mask CD Interrupt
MCDxy = 0
CDxy bit is NOT MASKED
MCDxy = 1*
CDxy bit is MASKED
x
Bit number (A or B)
y
Channel number (1 through 4)
Masked: A change does not cause the Interrupt Pin to go Low.
This command does not depend on the state of the Channel Enable Register.
* Power Up and Hardware Reset (RST) Value = FFh.
28, 29. Write/Read Operating Conditions
MPI Command
(70/71h)
R/W = 0: Write
R/W = 1: Read
Cutoff Transmit Path
CTP = 0*
Transmit path connected
CTP = 1
Transmit path cut off
Cutoff Receive Path
CRP = 0*
Receive path connected
CRP = 1
Receive path cutoff (see note)
High Pass Filter
HPF = 0*
Transmit Highpass filter enabled
HPF = 1
Transmit Highpass filter disabled
Lower Receive Gain
RG = 0*
6 dB loss not inserted
RG = 1
6 dB loss inserted
Arm Transmit Interrupt
ATI = 0*
Transmit Interrupt not Armed
ATI = 1
Transmit Interrupt Armed
Interface Loopback
ILB = 0*
TSA loopback disabled
ILB = 1
TSA loopback enabled
Full Digital Loopback
FDL = 0*
Full digital loopback disabled
FDL = 1
Full digital loopback enabled
1 kHz Receive Tone
TON = 0*
1 kHz receive tone off
TON = 1
1 kHz receive tone on
* Power Up and Hardware Reset (RST) Value = 00h.
The B Filter is disabled during receive cutoff.
D7
D6
D5
D4
D3
D2
D1
D0
Command
0
1
1
0
1
1
0
R/W
I/O Data
MCDB4
MCDA4
MCDB3
MCDA3
MCDB2
MCDA2
MCDB1
MCDA1
D7
D6
D5
D4
D3
D2
D1
D0
Command
0
1
1
1
0
0
0
R/W
I/O Data
CTP
CRP
HPF
RG
ATI
ILB
FDL
TON
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